/*******************************************************************************
 *
 * $Id: $
 * Copyright: (c) 2018 Broadcom. All Rights Reserved. "Broadcom" refers to 
 * Broadcom Limited and/or its subsidiaries.
 * 
 * Broadcom Switch Software License
 * 
 * This license governs the use of the accompanying Broadcom software. Your 
 * use of the software indicates your acceptance of the terms and conditions 
 * of this license. If you do not agree to the terms and conditions of this 
 * license, do not use the software.
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 *    grants to you a perpetual, worldwide, non-exclusive, and royalty-free 
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 *    intended for use, with a Broadcom switch integrated circuit.
 *    No Reverse Engineering. You will not use the Work to disassemble, 
 *    reverse engineer, decompile, or attempt to ascertain the underlying 
 *    technology of a Broadcom switch integrated circuit.
 * 8. Termination
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 *    license (including the license grants of Sections 2 and 3) will 
 *    terminate immediately.
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 * 10. Limitation of Liability
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 * 
 *
 * DO NOT EDIT THIS FILE!
 * This file is auto-generated from the registers file.
 * Edits to this file will be lost when it is regenerated.
 *
 * Symbol table file for the BCMI_TSCF_XGXS.
 * This symbol table is used by the Broadcom debug shell.
 */


#include <phymod/chip/bcmi_tscf_xgxs_gen2_defs.h>
#include <phymod/phymod_symbols.h>

/* No symbols will be compiled unless this is defined. */
#if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1
/*******************************************************************************
 *
 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information
 * necessary to encode and decode the individual fields of a register or memory
 * will be available.
 *
 * Without it, only the register and memory names will be symbolically available
 * and their values will be displayed as raw data only. 
 *
 * Field information can be compiled out in the interest of saving code space.
 */
#if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS

static uint32_t BCMI_TSCF_XGXS_ACC_ADDR_DATA_GEN2r_fields[] =
{
    /* MDIO_ADDR_DATA:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(977, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_ACC_CTL_GEN2r_fields[] =
{
    /* MDIO_DEVAD:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(981, 4, 0),
    /* MDIO_FUNCTION:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(988, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_0_GEN2r_fields[] =
{
    /* AMS_PLL_SET_CLK4TSC:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(87, 1, 0),
    /* AMS_PLL_IMIN_ICLKINT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(52, 2, 2),
    /* AMS_PLL_IMAX_ICLKINT:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(41, 3, 3),
    /* AMS_PLL_IMODE_ICLKINT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(63, 4, 4),
    /* AMS_PLL_IMIN_ICLKODRV1:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(53, 5, 5),
    /* AMS_PLL_IMAX_ICLKODRV1:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(42, 6, 6),
    /* AMS_PLL_IMODE_ICLKODRV1:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(64, 7, 7),
    /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(51, 8, 8),
    /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(40, 9, 9),
    /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(62, 10, 10),
    /* AMS_PLL_CAL_OFF:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(30, 11, 11),
    /* AMS_PLL_CAL_AUX:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(29, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_1_GEN2r_fields[] =
{
    /* AMS_PLL_IMIN_ICKGEN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(50, 0, 0),
    /* AMS_PLL_IMAX_ICKGEN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(39, 1, 1),
    /* AMS_PLL_IMODE_ICKGEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(61, 2, 2),
    /* AMS_PLL_DRV_HV_DISABLE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(32, 3, 3),
    /* AMS_PLL_TEST_BG_OPAMP_BIAS:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(91, 5, 4),
    /* AMS_PLL_SPARE_23_22:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(90, 7, 6),
    /* AMS_PLL_VCOICTRL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(99, 9, 8),
    /* AMS_PLL_VCO_INDICATOR:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(100, 10, 10),
    /* AMS_PLL_IVCO:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(71, 13, 11),
    /* AMS_PLL_RESET:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(86, 14, 14),
    /* AMS_PLL_ENABLE_FTUNE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(33, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_2_GEN2r_fields[] =
{
    /* AMS_PLL_EN_HRZ:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(34, 0, 0),
    /* AMS_PLL_IQP:1:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(70, 4, 1),
    /* AMS_PLL_REFL_PLL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(85, 5, 5),
    /* AMS_PLL_REFH_PLL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(84, 6, 6),
    /* AMS_PLL_IMIN_IBIAS:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(48, 7, 7),
    /* AMS_PLL_IMODE_IBIAS:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(59, 8, 8),
    /* AMS_PLL_IMAX_IBIAS:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(37, 9, 9),
    /* AMS_PLL_IMIN_ICP:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(56, 10, 10),
    /* AMS_PLL_IMODE_ICP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(67, 11, 11),
    /* AMS_PLL_IMAX_ICP:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(45, 12, 12),
    /* AMS_PLL_IMIN_ICK:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(49, 13, 13),
    /* AMS_PLL_IMODE_ICK:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(60, 14, 14),
    /* AMS_PLL_IMAX_ICK:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(38, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_3_GEN2r_fields[] =
{
    /* AMS_PLL_IMIN_IRXCLKBUF:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(58, 0, 0),
    /* AMS_PLL_IMODE_IRXCLKBUF:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(69, 1, 1),
    /* AMS_PLL_IMAX_IRXCLKBUF:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(47, 2, 2),
    /* AMS_PLL_IMIN_ICMLDIV:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(54, 3, 3),
    /* AMS_PLL_IMODE_ICMLDIV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(65, 4, 4),
    /* AMS_PLL_IMAX_ICMLDIV:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(43, 5, 5),
    /* AMS_PLL_IMIN_ICOMP:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(55, 6, 6),
    /* AMS_PLL_IMODE_ICOMP:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(66, 7, 7),
    /* AMS_PLL_IMAX_ICOMP:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(44, 8, 8),
    /* AMS_PLL_IMIN_IOP:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(57, 9, 9),
    /* AMS_PLL_IMODE_IOP:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(68, 10, 10),
    /* AMS_PLL_IMAX_IOP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(46, 11, 11),
    /* AMS_PLL_TEST_VREF:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(97, 12, 12),
    /* AMS_PLL_TEST_VC:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(96, 13, 13),
    /* AMS_PLL_TEST_PLL:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(92, 14, 14),
    /* AMS_PLL_TEST_RX:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(95, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_4_GEN2r_fields[] =
{
    /* AMS_PLL_BGR_PTATADJ:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(28, 3, 0),
    /* AMS_PLL_BGR_CTATADJ:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(27, 7, 4),
    /* AMS_PLL_PLL2RX_CLKBW:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(82, 9, 8),
    /* AMS_PLL_COMP_VTH:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(31, 10, 10),
    /* AMS_PLL_VDDR_BGB:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(101, 11, 11),
    /* AMS_PLL_KVH_FORCE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(73, 13, 12),
    /* AMS_PLL_FORCE_KVH_BW:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(35, 14, 14),
    /* AMS_PLL_FORCE_RESCAL:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(36, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_5_GEN2r_fields[] =
{
    /* AMS_PLL_TEST_PORT_MAX_AMPLITUDE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(94, 0, 0),
    /* AMS_PLL_BGIP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(26, 1, 1),
    /* AMS_PLL_BGINT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(25, 2, 2),
    /* AMS_PLL_VBYPASS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(98, 3, 3),
    /* AMS_PLL_TEST_PNP:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(93, 5, 4),
    /* AMS_PLL_MIX3P1C_CALR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(79, 10, 6),
    /* AMS_PLL_MIX3P1C_CALR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(80, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_6_GEN2r_fields[] =
{
    /* AMS_PLL_SPARE_101_96:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(88, 5, 0),
    /* AMS_PLL_MIX1P2CR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(75, 10, 6),
    /* AMS_PLL_MIX1P2CR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(76, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_CTL_7_GEN2r_fields[] =
{
    /* AMS_PLL_SPARE_117_112:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(89, 5, 0),
    /* AMS_PLL_MIX3P1CR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(77, 10, 6),
    /* AMS_PLL_MIX3P1CR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(78, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_AMS_PLL_STS_GEN2r_fields[] =
{
    /* AMS_PLL_NDIV:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(81, 3, 0),
    /* AMS_PLL_LOW:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(74, 5, 5),
    /* AMS_PLL_RANGE:6:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(83, 13, 6),
    /* AMS_PLL_KVH:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(72, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_0_GEN2r_fields[] =
{
    /* AMS_RX_MASTER_DIODES_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(120, 2, 0),
    /* AMS_RX_SIGDET_THRESHOLD:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(140, 5, 3),
    /* AMS_RX_SIGDET_PWRDN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(139, 6, 6),
    /* AMS_RX_SIGDET_BYPASS:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(136, 7, 7),
    /* AMS_RX_TPORT_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(153, 8, 8),
    /* AMS_RX_VGA_10G_BW:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(162, 9, 9),
    /* AMS_RX_EQ_LZ_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(118, 10, 10),
    /* AMS_RX_DFE_HGAIN_EN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(111, 11, 11),
    /* AMS_RX_DC_COUPLE:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(108, 12, 12),
    /* AMS_RX_PEAKING_FILTER_IBIAS:13:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(125, 15, 13)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_1_GEN2r_fields[] =
{
    /* AMS_RX_SPARE_16:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(147, 0, 0),
    /* AMS_RX_VGA0_IBIAS:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(154, 3, 1),
    /* AMS_RX_VGA1_IBIAS:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(156, 6, 4),
    /* AMS_RX_VGA2_IBIAS:7:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(158, 9, 7),
    /* AMS_RX_VGA3_IBIAS:10:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(160, 12, 10),
    /* AMS_RX_CM_VOLTAGE_IBIAS:13:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(103, 15, 13)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_2_GEN2r_fields[] =
{
    /* AMS_RX_SIGDET_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(137, 2, 0),
    /* AMS_RX_PHASE_INTERPOLATORS_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(128, 5, 3),
    /* AMS_RX_DFE_TAP_WEIGHT_IBIAS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(115, 8, 6),
    /* AMS_RX_SEL_UGBW:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(133, 10, 9),
    /* AMS_RX_SEL_TH4DFE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(132, 12, 11),
    /* AMS_RX_PD_CH_P1:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(124, 13, 13),
    /* AMS_RX_SIGDET_POWER_SAVE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(138, 14, 14),
    /* AMS_RX_PWRDN_FTAP:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(129, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_3_GEN2r_fields[] =
{
    /* AMS_RX_MET_R_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(121, 2, 0),
    /* AMS_RX_DLL_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(116, 5, 3),
    /* AMS_RX_OFFSET_CORRECTION_IBIAS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(122, 8, 6),
    /* AMS_RX_DFE_SUM_BUF_IBIAS:9:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(114, 11, 9),
    /* AMS_RX_DFE_SLICER_IBIAS:12:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(113, 14, 12),
    /* AMS_RX_SPARE_63:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(148, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_4_GEN2r_fields[] =
{
    /* AMS_RX_DFE_SLICER_CAL_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(112, 2, 0),
    /* AMS_RX_TBD_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(152, 5, 3),
    /* AMS_RX_VGA0_RESCAL_MUX:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(155, 10, 6),
    /* AMS_RX_VGA1_RESCAL_MUX:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(157, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_5_GEN2r_fields[] =
{
    /* AMS_RX_VGA2_RESCAL_MUX:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(159, 4, 0),
    /* AMS_RX_VGA3_RESCAL_MUX:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(161, 9, 5),
    /* AMS_RX_SPARE_94_90:10:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(149, 14, 10),
    /* AMS_RX_SPARE_95:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(150, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_6_GEN2r_fields[] =
{
    /* AMS_RX_PEAKING_FILTER_RESCAL_MUX:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(126, 3, 0),
    /* AMS_RX_OFFSET_CORRECTION_RESCAL_MUX:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(123, 7, 4),
    /* AMS_RX_SPARE_111_104:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(141, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_7_GEN2r_fields[] =
{
    /* AMS_RX_DC_OFFSET:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(109, 6, 0),
    /* AMS_RX_FORCE_DC_OFFSET:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(119, 7, 7),
    /* AMS_RX_DC_OFFSET_RANGE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(110, 8, 8),
    /* AMS_RX_RX_OFFSET_PD:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(130, 9, 9),
    /* AMS_RX_SHORT_VGA_OUTPUT:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(134, 10, 10),
    /* AMS_RX_SPARE_123:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(142, 11, 11),
    /* AMS_RX_VGA_LOW_GAIN:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(164, 13, 12),
    /* AMS_RX_VGA_STEP_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(165, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_8_GEN2r_fields[] =
{
    /* AMS_RX_DAC4CK_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(106, 5, 0),
    /* AMS_RX_SPARE_135_134:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(143, 7, 6),
    /* AMS_RX_DAC4CK_PHS:8:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(107, 13, 8),
    /* AMS_RX_SPARE_143_142:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(144, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_CTL_9_GEN2r_fields[] =
{
    /* AMS_RX_DAC4CK_DAT:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 0),
    /* AMS_RX_SPARE_151_150:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(145, 7, 6),
    /* AMS_RX_CLK_BW_CTRL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(102, 9, 8),
    /* AMS_RX_EN_TAP9DELAY:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(117, 10, 10),
    /* AMS_RX_SEL_D2CLP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(131, 11, 11),
    /* AMS_RX_D2C_CLKBUF_IBIAS:12:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(104, 14, 12),
    /* AMS_RX_SPARE_159:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(146, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_RX_STS_GEN2r_fields[] =
{
    /* AMS_RX_VGA_CTRL_GRAY:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(163, 4, 0),
    /* AMS_RX_TAP1_DATA_THRESH_SEL_GRAY:5:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(151, 10, 5),
    /* AMS_RX_PF_CTRL_GRAY:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(127, 14, 11),
    /* AMS_RX_SIGDET:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(135, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL_0_GEN2r_fields[] =
{
    /* AMS_TX_SPARE_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(185, 0, 0),
    /* AMS_TX_SPARE_3_1:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(188, 3, 1),
    /* AMS_TX_TEST_DATA:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(190, 5, 4),
    /* AMS_TX_TICKSEL:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(191, 7, 6),
    /* AMS_TX_VDDR_BGB:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(192, 8, 8),
    /* AMS_TX_DCC_SEL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(171, 9, 9),
    /* AMS_TX_DCC_DIS:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(170, 10, 10),
    /* AMS_TX_CAL_OFF:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(169, 11, 11),
    /* AMS_TX_CAL_AUX:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(168, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL_1_GEN2r_fields[] =
{
    /* AMS_TX_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(175, 2, 0),
    /* AMS_TX_SPARE_21_19:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(186, 5, 3),
    /* AMS_TX_ICML:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(176, 8, 6),
    /* AMS_TX_ILDO:9:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(177, 11, 9),
    /* AMS_TX_LDO_VREF:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(179, 13, 12),
    /* AMS_TX_SEL_EMPH_MODE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(182, 14, 14),
    /* AMS_TX_SPARE_31:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(187, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL_2_GEN2r_fields[] =
{
    /* AMS_TX_AMP_CTL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(166, 3, 0),
    /* AMS_TX_POST3_COEF:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(181, 6, 4),
    /* AMS_TX_SIGN_POST3:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(184, 7, 7),
    /* AMS_TX_POST2_COEF:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(180, 11, 8),
    /* AMS_TX_SIGN_POST2:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(183, 12, 12),
    /* AMS_TX_DRIVERMODE:13:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(172, 14, 13),
    /* AMS_TX_ELEC_IDLE_AUX:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(174, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AMS_TX_CTL_3_GEN2r_fields[] =
{
    /* AMS_TX_SPARE_63_48:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(189, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AMS_TX_STS_GEN2r_fields[] =
{
    /* AMS_TX_VERSION_ID:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(193, 7, 0),
    /* AMS_TX_ANA_RESCAL:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(167, 11, 8),
    /* AMS_TX_DRV_HV_DISABLE:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(173, 12, 12),
    /* AMS_TX_LANE_ID:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(178, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_0_GEN2r_fields[] =
{
    /* AN_PRIORITY_100G_CR4:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(247, 1, 0),
    /* AN_PRIORITY_100G_HG2_CR4:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(248, 3, 2),
    /* AN_PRIORITY_100G_KR4:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(250, 5, 4),
    /* AN_PRIORITY_100G_HG2_KR4:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(249, 7, 6),
    /* AN_PRIORITY_40G_CR4:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(271, 9, 8),
    /* AN_PRIORITY_40G_HG2_CR4:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(273, 11, 10),
    /* AN_PRIORITY_40G_KR4:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(277, 13, 12),
    /* AN_PRIORITY_40G_HG2_KR4:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(275, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_1_GEN2r_fields[] =
{
    /* AN_PRIORITY_50G_CR4:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(279, 1, 0),
    /* AN_PRIORITY_50G_HG2_CR4:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(281, 3, 2),
    /* AN_PRIORITY_50G_KR4:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(285, 5, 4),
    /* AN_PRIORITY_50G_HG2_KR4:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(283, 7, 6),
    /* AN_PRIORITY_50G_CR2:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(278, 9, 8),
    /* AN_PRIORITY_50G_HG2_CR2:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(280, 11, 10),
    /* AN_PRIORITY_50G_KR2:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(284, 13, 12),
    /* AN_PRIORITY_50G_HG2_KR2:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(282, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_2_GEN2r_fields[] =
{
    /* AN_PRIORITY_40G_CR2:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(270, 1, 0),
    /* AN_PRIORITY_40G_HG2_CR2:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(272, 3, 2),
    /* AN_PRIORITY_40G_KR2:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(276, 5, 4),
    /* AN_PRIORITY_40G_HG2_KR2:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(274, 7, 6),
    /* AN_PRIORITY_25G_CR1:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(262, 9, 8),
    /* AN_PRIORITY_25G_HG2_CR1:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(265, 11, 10),
    /* AN_PRIORITY_25G_KR1:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(267, 13, 12),
    /* AN_PRIORITY_25G_HG2_KR1:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(266, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_3_GEN2r_fields[] =
{
    /* AN_PRIORITY_20G_CR1:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(254, 1, 0),
    /* AN_PRIORITY_20G_HG2_CR1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(256, 3, 2),
    /* AN_PRIORITY_20G_KR1:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(260, 5, 4),
    /* AN_PRIORITY_20G_HG2_KR1:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(258, 7, 6),
    /* AN_PRIORITY_20G_CR2:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(255, 9, 8),
    /* AN_PRIORITY_20G_HG2_CR2:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(257, 11, 10),
    /* AN_PRIORITY_20G_KR2:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(261, 13, 12),
    /* AN_PRIORITY_20G_HG2_KR2:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(259, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_4_GEN2r_fields[] =
{
    /* AN_PRIORITY_10G_KR1:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(252, 1, 0),
    /* AN_PRIORITY_10G_HG2_KR1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(251, 3, 2),
    /* AN_PRIORITY_1G_KX1:4:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(253, 5, 4)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNK_GEN2r_fields[] =
{
    /* CL73_BREAK_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(456, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCK_GEN2r_fields[] =
{
    /* PD_DME_LOCK_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1128, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_CL73_ERR_GEN2r_fields[] =
{
    /* CL73_ERROR_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(458, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPE_GEN2r_fields[] =
{
    /* CL73_PAGE_TEST_MIN_TIMER:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(464, 6, 0),
    /* CL73_PAGE_TEST_MAX_TIMER:7:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(463, 13, 7)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_GLB_INT_GEN2r_fields[] =
{
    /* INT_PORT0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(874, 0, 0),
    /* INT_PORT1:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(876, 1, 1),
    /* INT_PORT2:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(878, 2, 2),
    /* INT_PORT3:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(880, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_GLB_MASK_GEN2r_fields[] =
{
    /* INT_PORT0_MASK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(875, 0, 0),
    /* INT_PORT1_MASK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(877, 1, 1),
    /* INT_PORT2_MASK:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(879, 2, 2),
    /* INT_PORT3_MASK:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(881, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_IEEE_SPD_PRI_1_GEN2r_fields[] =
{
    /* AN_PRIORITY_25G_CR1_IEEE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(263, 1, 0),
    /* AN_PRIORITY_25G_CRS1_IEEE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(264, 3, 2),
    /* AN_PRIORITY_25G_KR1_IEEE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(268, 5, 4),
    /* AN_PRIORITY_25G_KRS1_IEEE:6:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(269, 7, 6)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMR_GEN2r_fields[] =
{
    /* IGNORE_LINK_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(870, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72_GEN2r_fields[] =
{
    /* LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(917, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72_GEN2r_fields[] =
{
    /* LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(918, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_OUI_LWR_GEN2r_fields[] =
{
    /* OUI_LOWER_DATA:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1102, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_OUI_UPR_GEN2r_fields[] =
{
    /* OUI_UPPER_DATA:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1103, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X1_PD_SD_TMR_GEN2r_fields[] =
{
    /* PD_SD_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1131, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STS_GEN2r_fields[] =
{
    /* AN_HCD_CL72:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(237, 0, 0),
    /* AN_HCD_FEC:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(239, 1, 1),
    /* AN_HCD_SPEED:2:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(242, 9, 2),
    /* AN_HCD_PAUSE:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(240, 11, 10),
    /* AN_HCD_DUPLEX:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(238, 12, 12),
    /* HCD_CL91_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(843, 13, 13),
    /* HCD_DBG_CL74_UP_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(845, 14, 14),
    /* HCD_DBG_CL74_BASE_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(844, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_AN_MISC_STS_GEN2r_fields[] =
{
    /* PD_IN_PROGRESS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1129, 1, 1),
    /* AN_FAIL_COUNT:2:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(229, 5, 2),
    /* AN_ACTIVE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(223, 6, 6),
    /* PD_COMPLETED:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1127, 7, 7),
    /* SPEED_FORCE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1493, 8, 8),
    /* AN_RETRY_COUNT:9:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(286, 14, 9),
    /* AN_COMPLETE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(224, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_CL73_CFG_GEN2r_fields[] =
{
    /* CL73_AN_RESTART:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(452, 0, 0),
    /* AD_TO_CL73_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(3, 2, 2),
    /* BAM_TO_HPAM_AD_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(301, 3, 3),
    /* CL73_NONCE_MATCH_VAL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(462, 5, 5),
    /* CL73_NONCE_MATCH_OVER:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(461, 6, 6),
    /* CL73_ENABLE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(457, 8, 8),
    /* CL73_HPAM_ENABLE:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(460, 9, 9),
    /* CL73_BAM_ENABLE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(454, 10, 10),
    /* NUM_ADVERTISED_LANES:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1075, 12, 11),
    /* DISABLE_REMOTE_FAULT:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(730, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_CL73_CTLS_GEN2r_fields[] =
{
    /* PD_KX_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1130, 1, 1),
    /* AN_GOOD_TRAP:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(236, 2, 2),
    /* AN_GOOD_CHECK_TRAP:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(233, 3, 3),
    /* LINKFAILTIMER_DIS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(916, 4, 4),
    /* LINKFAILTIMERQUAL_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(915, 5, 5),
    /* AN_FAIL_COUNT_LIMIT:6:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(230, 9, 6),
    /* AN_OUI_OVERRIDE_HPAM_DET:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(246, 12, 12),
    /* AN_OUI_OVERRIDE_HPAM_ADV:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(245, 13, 13),
    /* AN_OUI_OVERRIDE_BAM73_DET:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(244, 14, 14),
    /* AN_OUI_OVERRIDE_BAM73_ADV:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(243, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_INT_EN_GEN2r_fields[] =
{
    /* LP_PAGE_RDY_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(970, 0, 0),
    /* LD_PAGE_REQ_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(912, 1, 1),
    /* AN_COMPLETED_SW_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(226, 2, 2),
    /* AN_GOOD_CHK_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(234, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_INT_GEN2r_fields[] =
{
    /* LP_PAGE_RDY_INT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(971, 0, 0),
    /* LD_PAGE_REQ_INT:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(913, 1, 1),
    /* AN_COMPLETED_SW_INT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(227, 2, 2),
    /* AN_GOOD_CHK_INT:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(235, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABIL_GEN2r_fields[] =
{
    /* CL73_BAM_CODE:0:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(453, 8, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_0_GEN2r_fields[] =
{
    /* CL73_BASE_SELECTOR:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(455, 4, 0),
    /* TX_NONCE:5:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1629, 9, 5)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_1_GEN2r_fields[] =
{
    /* BASE_10G_KR1:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(304, 0, 0),
    /* BASE_40G_KR4:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(315, 1, 1),
    /* BASE_40G_CR4:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(314, 2, 2),
    /* BASE_100G_KR4:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(303, 3, 3),
    /* BASE_100G_CR4:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(302, 4, 4),
    /* BASE_1G_KX1:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(305, 5, 5),
    /* CL73_PAUSE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(465, 7, 6),
    /* FEC_REQ:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(823, 9, 8),
    /* NEXT_PAGE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1072, 10, 10),
    /* CL73_REMOTE_FAULT:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(466, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_2_GEN2r_fields[] =
{
    /* BASE_50G_CR2_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(316, 0, 0),
    /* BASE_50G_CR2_SEL:1:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(317, 5, 1),
    /* BASE_50G_KR2_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(318, 6, 6),
    /* BASE_50G_KR2_SEL:7:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(319, 11, 7)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_3_GEN2r_fields[] =
{
    /* BASE_25G_CR1_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(306, 0, 0),
    /* BASE_25G_CR1_SEL:1:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(307, 5, 1),
    /* BASE_25G_KR1_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(310, 6, 6),
    /* BASE_25G_KR1_SEL:7:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(311, 11, 7)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_4_GEN2r_fields[] =
{
    /* BASE_25G_CRS1_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(308, 0, 0),
    /* BASE_25G_CRS1_SEL:1:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(309, 5, 1),
    /* BASE_25G_KRS1_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(312, 6, 6),
    /* BASE_25G_KRS1_SEL:7:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(313, 11, 7)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_CTL_GEN2r_fields[] =
{
    /* AN_HCD_RES_DISABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(241, 0, 0),
    /* AN_TYPE_SW:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(287, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_fields[] =
{
    /* RS_FEC_REQ_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1268, 0, 0),
    /* RS_FEC_REQ_SEL:1:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1269, 5, 1),
    /* BASE_R_FEC_REQ_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(320, 6, 6),
    /* BASE_R_FEC_REQ_SEL:7:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(321, 11, 7)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE_0_GEN2r_fields[] =
{
    /* LD_PAGE_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(908, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE_1_GEN2r_fields[] =
{
    /* LD_PAGE_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(909, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_PAGE_2_GEN2r_fields[] =
{
    /* LD_PAGE_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(910, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_0_GEN2r_fields[] =
{
    /* BAM_20G_KR2:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(291, 0, 0),
    /* BAM_20G_CR2:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(289, 1, 1),
    /* BAM_40G_KR2:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(295, 2, 2),
    /* BAM_40G_CR2:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(294, 3, 3),
    /* BAM_50G_KR2:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(298, 6, 6),
    /* BAM_50G_CR2:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(296, 7, 7),
    /* BAM_50G_KR4:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(299, 8, 8),
    /* BAM_50G_CR4:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(297, 9, 9),
    /* BAM_HG2:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(300, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_1_GEN2r_fields[] =
{
    /* BAM_20G_KR1:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(290, 1, 1),
    /* BAM_20G_CR1:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(288, 2, 2),
    /* BAM_25G_KR1:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(293, 3, 3),
    /* BAM_25G_CR1:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(292, 4, 4),
    /* CL91_REQ:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(551, 13, 12),
    /* CL74_REQ:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(468, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE1_GEN2r_fields[] =
{
    /* LP_BASE1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(958, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE2_GEN2r_fields[] =
{
    /* LP_BASE2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(959, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_BASE3_GEN2r_fields[] =
{
    /* LP_BASE3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(960, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1_GEN2r_fields[] =
{
    /* LP_OUI_UP1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(961, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2_GEN2r_fields[] =
{
    /* LP_OUI_UP2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(962, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3_GEN2r_fields[] =
{
    /* LP_OUI_UP3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(963, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4_GEN2r_fields[] =
{
    /* LP_OUI_UP4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(964, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5_GEN2r_fields[] =
{
    /* LP_OUI_UP5:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(965, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE_0_GEN2r_fields[] =
{
    /* LP_PAGE_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(966, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE_1_GEN2r_fields[] =
{
    /* LP_PAGE_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(967, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_LP_PAGE_2_GEN2r_fields[] =
{
    /* LP_PAGE_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(968, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_PSEQ_RF_GEN2r_fields[] =
{
    /* REMOTE_FAULT_SET:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1227, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_PSEQ_STS_GEN2r_fields[] =
{
    /* HP_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(859, 0, 0),
    /* RX_BP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1380, 1, 1),
    /* RX_NP:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1404, 2, 2),
    /* RX_MP_NULL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1401, 3, 3),
    /* RX_MP_OUI:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1402, 4, 4),
    /* RX_MP_MISMATCH:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1400, 5, 5),
    /* RX_UP_OUI_MISMATCH:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1432, 6, 6),
    /* RX_UP_OUI_MATCH:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1431, 7, 7),
    /* RX_INVALID_SEQ:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1392, 8, 8),
    /* RX_NP_TOGGLE_ERR:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1405, 9, 9),
    /* CL73_AN_COMPLETE:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(451, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_PXNG_STS_GEN2r_fields[] =
{
    /* CONSISTENCY_MISMATCH:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(608, 0, 0),
    /* COMPLETE_ACK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(607, 1, 1),
    /* ACK_DETECT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1, 2, 2),
    /* ABILITY_DETECT:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(0, 3, 3),
    /* AN_ENABLE:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(228, 4, 4),
    /* ERROR_STATE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(778, 5, 5),
    /* TRANSMIT_DISABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1537, 6, 6),
    /* NEXT_PAGE_WAIT:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1073, 7, 7),
    /* AN_GOOD_CHECK:8:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(232, 8, 8)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_RES_ERR_GEN2r_fields[] =
{
    /* RESOLUTION_ERROR:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1232, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_R_CL73_STS_GEN2r_fields[] =
{
    /* DME_STATE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(736, 1, 0),
    /* DME_PAGE:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(735, 2, 2),
    /* DME_MV_PAIR:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(734, 3, 3),
    /* CLK_TRANS_MISS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(599, 4, 4),
    /* PAGE_TOO_LONG:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1104, 5, 5),
    /* PAGE_TOO_SHORT:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1105, 6, 6),
    /* PULSE_TOO_LONG:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1216, 7, 7),
    /* PULSE_TOO_MODERATE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1217, 8, 8),
    /* PULSE_TOO_SHORT:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1218, 9, 9),
    /* DME_LOCKED:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(733, 10, 10),
    /* CL73_FIFO_FULL:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(459, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_0_GEN2r_fields[] =
{
    /* SW_AN_BP_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1498, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_1_GEN2r_fields[] =
{
    /* SW_AN_BP_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1499, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_2_GEN2r_fields[] =
{
    /* SW_AN_BP_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1500, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_SW_CTL_STS_GEN2r_fields[] =
{
    /* TLA_LN_SEQUENCER_FSM_STATUS1:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1533, 7, 0),
    /* PD_CL37_COMPLETED:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1126, 8, 8),
    /* LD_SEQ_RESTART:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(914, 11, 11),
    /* LP_PAGE_RDY:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(969, 12, 12),
    /* LD_PAGE_REQ:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(911, 13, 13),
    /* LD_CONTROL_VALID:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(907, 14, 14),
    /* AN_COMPLETED:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(225, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STS_GEN2r_fields[] =
{
    /* TLA_SEQ_FSM_STATUS:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1534, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGE_GEN2r_fields[] =
{
    /* RX_UNEXPECTED_PAGE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1430, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_AN_X4_WAIT_ACK_COMPLETE_GEN2r_fields[] =
{
    /* WAIT_FOR_ACK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1731, 0, 0),
    /* SEND_ACK:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1467, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTL_GEN2r_fields[] =
{
    /* LN_RX_S_CLKGATE_FRC_ON:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(930, 0, 0),
    /* LN_RX_S_COMCLK_SEL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(932, 1, 1),
    /* LN_RX_S_COMCLK_FRC_ON:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(931, 2, 2),
    /* PMD_RX_CLK_VLD_FRC:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1172, 3, 3),
    /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1173, 4, 4)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_GEN2r_fields[] =
{
    /* AFE_RX_PWRDN_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(4, 0, 0),
    /* AFE_RX_PWRDN_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(5, 1, 1),
    /* AFE_RX_RESET_FRC:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(8, 2, 2),
    /* AFE_RX_RESET_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(9, 3, 3),
    /* AFE_TX_PWRDN_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(16, 4, 4),
    /* AFE_TX_PWRDN_FRC_VAL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(17, 5, 5),
    /* AFE_TX_RESET_FRC:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(18, 6, 6),
    /* AFE_TX_RESET_FRC_VAL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(19, 7, 7),
    /* AFE_RX_RCLK20_PWRDN_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(6, 8, 8),
    /* AFE_RX_RCLK20_PWRDN_FRC_VAL:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(7, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTL_GEN2r_fields[] =
{
    /* LN_DP_S_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(926, 1, 1),
    /* LN_RX_S_PWRDN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(933, 2, 2),
    /* LN_TX_S_PWRDN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(938, 3, 3),
    /* AFE_SIGDET_PWRDN:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(10, 4, 4)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTL_GEN2r_fields[] =
{
    /* LN_RX_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(934, 0, 0),
    /* LN_RX_DP_S_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(928, 1, 1),
    /* SIGDET_DP_RSTB_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1471, 2, 2),
    /* LN_TX_S_RSTB:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(939, 8, 8),
    /* LN_TX_DP_S_RSTB:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(936, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STS_GEN2r_fields[] =
{
    /* LANE_DP_RESET_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(899, 2, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_MCST_MASK_CTL_GEN2r_fields[] =
{
    /* LANE_MULTICAST_MASK_CONTROL:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(902, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTL_GEN2r_fields[] =
{
    /* PMD_LN_H_RSTB_PKILL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1166, 0, 0),
    /* PMD_LN_DP_H_RSTB_PKILL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1165, 1, 1),
    /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1167, 2, 2),
    /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1168, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTL_GEN2r_fields[] =
{
    /* LANE_REG_RESET_OCCURRED:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(903, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTL_GEN2r_fields[] =
{
    /* LN_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(935, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTL_GEN2r_fields[] =
{
    /* OSR_MODE_FRC_VAL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1095, 3, 0),
    /* OSR_MODE_FRC:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1094, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STS_GEN2r_fields[] =
{
    /* OSR_MODE_PIN:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1097, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_OSR_MODE_STS_GEN2r_fields[] =
{
    /* OSR_MODE:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1093, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STS_GEN2r_fields[] =
{
    /* PMD_LANE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1164, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTL_GEN2r_fields[] =
{
    /* UC_ACK_LANE_CFG_DONE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1700, 0, 0),
    /* UC_ACK_LANE_DP_RESET:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1701, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_CL82_AM_TMR_GEN2r_fields[] =
{
    /* AM_TIMER_INIT_VAL:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(221, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL82_BER_HO_GEN2r_fields[] =
{
    /* BER_HO:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(325, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL82_BER_LO_GEN2r_fields[] =
{
    /* BER_LO:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(326, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HO_GEN2r_fields[] =
{
    /* ERRORED_BLOCKS_HO:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(769, 13, 0),
    /* ERRORED_BLOCKS_HO_PRESENT:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(770, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2_GEN2r_fields[] =
{
    /* LANE_0_AM_2:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(892, 7, 0),
    /* LANE_1_AM_2:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(894, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10_GEN2r_fields[] =
{
    /* LANE_0_AM_1_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(891, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10_GEN2r_fields[] =
{
    /* LANE_1_AM_1_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(893, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL82_RX_LATCH_STS_GEN2r_fields[] =
{
    /* DESKEW_HIS_STATE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(691, 1, 0),
    /* HISTORY_RXSM_STATE:2:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(850, 8, 2)
};
static uint32_t BCMI_TSCF_XGXS_CL82_RX_LIVE_STS_GEN2r_fields[] =
{
    /* CURRENT_RXSM_STATE:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(648, 6, 0),
    /* R_TYPE_CODED:7:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1452, 12, 7),
    /* DESKEW_STATE:13:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(706, 14, 13)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPD_152_GEN2r_fields[] =
{
    /* CL93N72_IEEE_LP_COEFF_UPDATE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(564, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REP_153_GEN2r_fields[] =
{
    /* CL93N72_IEEE_LP_STATUS_REPORT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(565, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPD_154_GEN2r_fields[] =
{
    /* CL93N72_IEEE_LD_COEFF_UPDATE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(562, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REP_155_GEN2r_fields[] =
{
    /* CL93N72_IEEE_LD_STATUS_REPORT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(563, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTL_150_GEN2r_fields[] =
{
    /* CL93N72_IEEE_RESTART_TRAINING:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(567, 0, 0),
    /* CL93N72_IEEE_TRAINING_ENABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STS_151_GEN2r_fields[] =
{
    /* CL93N72_IEEE_RECEIVER_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(566, 0, 0),
    /* CL93N72_IEEE_FRAME_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(561, 1, 1),
    /* CL93N72_IEEE_TRAINING_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(570, 2, 2),
    /* CL93N72_IEEE_TRAINING_FAILURE:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(569, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL0_GEN2r_fields[] =
{
    /* CL93N72_RX_TRAINING_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(585, 0, 0),
    /* CL93N72_TR_COARSE_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(592, 1, 1),
    /* CL93N72_RX_SIGNAL_OK:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(584, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL1_GEN2r_fields[] =
{
    /* CL93N72_GOOD_MARKER_CNT:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(560, 1, 0),
    /* CL93N72_BAD_MARKER_CNT:4:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(552, 6, 4)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_CTL2_GEN2r_fields[] =
{
    /* CL93N72_CTRL_FRAME_DLY:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(555, 3, 0),
    /* CL93N72_DME_CELL_BOUNDARY_CHK:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(557, 4, 4),
    /* CL93N72_STRICT_DME_CHK:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(586, 5, 5),
    /* CL93N72_STRICT_MARKER_CHK:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(587, 6, 6),
    /* CL93N72_PPM_OFFSET_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(579, 7, 7),
    /* CL93N72_RX_DP_LN_CLK_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(583, 8, 8),
    /* CL93N72_FRAME_CONSISTENCY_CHK_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_STS0_GEN2r_fields[] =
{
    /* CL93N72_FRAME_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(559, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0_GEN2r_fields[] =
{
    /* CL93N72_MICRO_UPDATE_CHG_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(577, 0, 0),
    /* CL93N72_MICRO_STATUS_CHG_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(575, 1, 1),
    /* CL93N72_MICRO_FRAME_LOCK_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0_GEN2r_fields[] =
{
    /* CL93N72_MICRO_UPDATE_CHG_LSTATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(578, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1_GEN2r_fields[] =
{
    /* CL93N72_MICRO_STATUS_CHG_LSTATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(576, 0, 0),
    /* CL93N72_MICRO_FRAME_LOCK_LSTATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(574, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL0_GEN2r_fields[] =
{
    /* CL93N72_SW_RX_TRAINED:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(590, 0, 0),
    /* CL93N72_SW_FRAME_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(588, 1, 1),
    /* CL93N72_SW_REMOTE_RX_READY:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(589, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL1_GEN2r_fields[] =
{
    /* CL93N72_BRK_RING_OSC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(553, 0, 0),
    /* CL93N72_DIS_MAX_WAIT_TIMER:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(556, 1, 1),
    /* CL93N72_TX_DP_LN_CLK_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(596, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL2_GEN2r_fields[] =
{
    /* CL93N72_TXFIR_PRE:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(595, 4, 0),
    /* CL93N72_TXFIR_POST:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(594, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL3_GEN2r_fields[] =
{
    /* CL93N72_TXFIR_MAIN:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(593, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_CTL4_GEN2r_fields[] =
{
    /* CL93N72_PRBS_SEED_VAL:0:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(582, 10, 0),
    /* CL93N72_CL93PRBS_POLY_SEL:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(554, 12, 11),
    /* CL93N72_PRBS_MODE_SEL:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(580, 13, 13),
    /* CL93N72_PRBS_SEED_SEL:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(581, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGE_GEN2r_fields[] =
{
    /* CL93N72_LD_XMT_STATUS_PAGE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(571, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_STS0_GEN2r_fields[] =
{
    /* CL93N72_LOCAL_RX_READY:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(572, 0, 0),
    /* CL93N72_TRAINING_FSM_SIGNAL_DETECT:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(591, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGE_GEN2r_fields[] =
{
    /* CL93N72_XMT_UPDATE_PAGE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(597, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STS_GEN2r_fields[] =
{
    /* CORE_DP_RESET_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(621, 2, 0),
    /* LANE_RESET_RELEASED_INDEX:8:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(905, 12, 8),
    /* LANE_RESET_RELEASED:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(904, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_DIG_CORE_MCST_MASK_CONRTOL_GEN2r_fields[] =
{
    /* CORE_MULTICAST_MASK_CONTROL:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(625, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTL_GEN2r_fields[] =
{
    /* CORE_REG_RESET_OCCURRED:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(626, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3_GEN2r_fields[] =
{
    /* LANE_ADDR_2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(897, 4, 0),
    /* LANE_ADDR_3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(898, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STS_GEN2r_fields[] =
{
    /* PMD_CORE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1163, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_REVID0_GEN2r_fields[] =
{
    /* REVID_MODEL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1250, 5, 0),
    /* REVID_PROCESS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1253, 8, 6),
    /* REVID_BONDING:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1244, 10, 9),
    /* REVID_REV_NUMBER:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1255, 13, 11),
    /* REVID_REV_LETTER:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1254, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DIG_REVID1_GEN2r_fields[] =
{
    /* REVID_EEE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1246, 0, 0),
    /* REVID_LLP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1247, 1, 1),
    /* REVID_PIR:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1252, 2, 2),
    /* REVID_CL72:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1245, 3, 3),
    /* REVID_MICRO:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1249, 4, 4),
    /* REVID_MDIO:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1248, 5, 5),
    /* REVID_MULTIPLICITY:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1251, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DIG_REVID2_GEN2r_fields[] =
{
    /* REVID2:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1243, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DP_GEN2r_fields[] =
{
    /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1162, 1, 1),
    /* SUP_RST_SEQ_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1497, 3, 3),
    /* SUP_RST_SEQ_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1496, 4, 4),
    /* PMD_MDIO_TRANS_PKILL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1171, 5, 5),
    /* PMD_TX_CLK_VLD_FRC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1176, 7, 7),
    /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1177, 8, 8),
    /* TX_S_COMCLK_SEL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1667, 9, 9),
    /* TX_S_COMCLK_FRC_ON:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1666, 10, 10),
    /* TX_S_CLKGATE_FRC_ON:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1665, 11, 11),
    /* AFE_S_PLL_RESET_FRC_VAL:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(15, 12, 12),
    /* AFE_S_PLL_RESET_FRC:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(14, 13, 13),
    /* TX_PI_LOOP_FILTER_STABLE:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1646, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_DIG_RST_CTL_PMD_GEN2r_fields[] =
{
    /* CORE_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(627, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTL_GEN2r_fields[] =
{
    /* RST_SEQ_TIMER:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1267, 2, 0),
    /* PWRDN_SEQ_TIMER:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1219, 10, 8),
    /* RST_SEQ_DIS_FLT_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1266, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DIG_TOP_USER_CTL_0_GEN2r_fields[] =
{
    /* HEARTBEAT_COUNT_1US:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(846, 9, 0),
    /* CORE_DP_S_RSTB:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(622, 13, 13),
    /* AFE_S_PLL_PWRDN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(13, 14, 14),
    /* UC_ACTIVE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1702, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2_GEN2r_fields[] =
{
    /* TX_LANE_MAP_0:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1619, 4, 0),
    /* TX_LANE_MAP_1:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1620, 9, 5),
    /* TX_LANE_MAP_2:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1621, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1_GEN2r_fields[] =
{
    /* TX_LANE_MAP_3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1622, 4, 0),
    /* LANE_ADDR_0:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(895, 9, 5),
    /* LANE_ADDR_1:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(896, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTL_GEN2r_fields[] =
{
    /* UC_ACK_CORE_CFG_DONE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1695, 0, 0),
    /* UC_ACK_CORE_DP_RESET:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1696, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_1G_STS_GEN2r_fields[] =
{
    /* CDR_1G_PHASE_POINTER:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(393, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL_0_GEN2r_fields[] =
{
    /* OS_ALL_EDGES:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1098, 0, 0),
    /* BR_PD_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(351, 1, 1),
    /* OS_PATTERN_ENHANCED:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1101, 2, 2),
    /* CDR_FREQ_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(402, 3, 3),
    /* CDR_INTEG_REG_CLR:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(408, 5, 5),
    /* CDR_PHASE_ERR_FRZ:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(413, 6, 6),
    /* CDR_INTEG_SAT_SEL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(409, 7, 7),
    /* CDR_FREQ_OVERRIDE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(403, 8, 8),
    /* CDR_ZERO_POLARITY:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL_1_GEN2r_fields[] =
{
    /* CDR_FREQ_OVERRIDE_VAL:5:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(404, 15, 5)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_CTL_2_GEN2r_fields[] =
{
    /* CDR_LM_THR_SEL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(411, 3, 0),
    /* CDR_1G_SWAP_PZ:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(394, 4, 4),
    /* CDR_1G_FORCE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(390, 5, 5),
    /* TX_PI_LOOP_TIMING_SRC_SEL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1647, 6, 6),
    /* PHS_SUM_IGNORE_DSC_LOCK:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1134, 7, 7),
    /* CDR_1G_MANUAL_MODE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(391, 8, 8),
    /* CDR_1G_MANUAL_STROBE:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(392, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_INTEG_GEN2r_fields[] =
{
    /* CDR_INTEG_REG:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(407, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_MISC_GEN2r_fields[] =
{
    /* CDR_LM_OUTOFLOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(410, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERR_GEN2r_fields[] =
{
    /* CDR_PHASE_ERROR:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(412, 5, 0),
    /* CDR_VCO_REG:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(415, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTL_GEN2r_fields[] =
{
    /* THRESH_TIMER_T1:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1524, 1, 0),
    /* THRESH_STEP_SIZE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1523, 5, 4),
    /* DATA_THRESH_SEL_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(649, 14, 8),
    /* DATA_THRESH_WRITE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(650, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_DC_OFFS_CTL_GEN2r_fields[] =
{
    /* DC_OFFS_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(671, 0, 0),
    /* DC_OFFS_HYS_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(674, 2, 2),
    /* DC_OFFS_HYS_MAG:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(675, 3, 3),
    /* DC_OFFS_GRADIENT_INVERT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(673, 4, 4),
    /* DC_OFFS_GAIN:5:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(672, 6, 5),
    /* DC_OFFS_ACC_CLR:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(670, 7, 7),
    /* DC_OFFS_WRITE_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(678, 14, 8),
    /* DC_OFFS_WRITE_FRC_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(677, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_DC_OFFS_STS_GEN2r_fields[] =
{
    /* DC_OFFSET_BIN:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(669, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_LOAD_PRESETS_GEN2r_fields[] =
{
    /* PRESET_DSC_AFE_BANK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1202, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_PRESET_GEN2r_fields[] =
{
    /* PRESET_DSC_C_BANK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1204, 0, 0),
    /* PRESET_DSC_D_BANK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1205, 1, 1),
    /* PRESET_DSC_A_BANK:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1203, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMS_GEN2r_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1319, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_LMS:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1293, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields[] =
{
    /* RXA_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1292, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1291, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields[] =
{
    /* RXA_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1295, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1294, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1318, 5, 0),
    /* RXB_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1317, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1321, 5, 0),
    /* RXB_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1320, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMS_GEN2r_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1371, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_LMS:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1345, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields[] =
{
    /* RXC_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1344, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1343, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields[] =
{
    /* RXC_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1347, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1346, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1370, 5, 0),
    /* RXD_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1369, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1373, 5, 0),
    /* RXD_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1372, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO_0_GEN2r_fields[] =
{
    /* RX_DATA_15_TO_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1386, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20_GEN2r_fields[] =
{
    /* RX_DATA_35_TO_20:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1387, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP10:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1348, 3, 0),
    /* RXC_DFE_TAP10:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1322, 7, 4),
    /* RXB_DFE_TAP10:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1296, 11, 8),
    /* RXA_DFE_TAP10:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1270, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP12_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1353, 1, 0),
    /* RXD_DFE_TAP11_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1351, 3, 2),
    /* RXC_DFE_TAP12_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1327, 5, 4),
    /* RXC_DFE_TAP11_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1325, 7, 6),
    /* RXB_DFE_TAP12_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1301, 9, 8),
    /* RXB_DFE_TAP11_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1299, 11, 10),
    /* RXA_DFE_TAP12_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1275, 13, 12),
    /* RXA_DFE_TAP11_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1273, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP11:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1350, 3, 0),
    /* RXC_DFE_TAP11:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1324, 7, 4),
    /* RXB_DFE_TAP11:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1298, 11, 8),
    /* RXA_DFE_TAP11:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1272, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP12:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1352, 3, 0),
    /* RXC_DFE_TAP12:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1326, 7, 4),
    /* RXB_DFE_TAP12:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1300, 11, 8),
    /* RXA_DFE_TAP12:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1274, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP14_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1357, 1, 0),
    /* RXD_DFE_TAP13_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1355, 3, 2),
    /* RXC_DFE_TAP14_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1331, 5, 4),
    /* RXC_DFE_TAP13_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1329, 7, 6),
    /* RXB_DFE_TAP14_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1305, 9, 8),
    /* RXB_DFE_TAP13_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1303, 11, 10),
    /* RXA_DFE_TAP14_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1279, 13, 12),
    /* RXA_DFE_TAP13_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1277, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP13:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1354, 3, 0),
    /* RXC_DFE_TAP13:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1328, 7, 4),
    /* RXB_DFE_TAP13:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1302, 11, 8),
    /* RXA_DFE_TAP13:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1276, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP14:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1356, 3, 0),
    /* RXC_DFE_TAP14:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1330, 7, 4),
    /* RXB_DFE_TAP14:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1304, 11, 8),
    /* RXA_DFE_TAP14:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1278, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_AB_GEN2r_fields[] =
{
    /* RXB_DFE_TAP2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1306, 4, 0),
    /* RXA_DFE_TAP2:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1280, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1358, 4, 0),
    /* RXC_DFE_TAP2:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1332, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_AB_GEN2r_fields[] =
{
    /* RXB_DFE_TAP3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1307, 4, 0),
    /* RXA_DFE_TAP3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1281, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1359, 4, 0),
    /* RXC_DFE_TAP3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1333, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP4:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1360, 3, 0),
    /* RXC_DFE_TAP4:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1334, 7, 4),
    /* RXB_DFE_TAP4:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1308, 11, 8),
    /* RXA_DFE_TAP4:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1282, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP5:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1361, 3, 0),
    /* RXC_DFE_TAP5:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1335, 7, 4),
    /* RXB_DFE_TAP5:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1309, 11, 8),
    /* RXA_DFE_TAP5:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1283, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP6:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1362, 3, 0),
    /* RXC_DFE_TAP6:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1336, 7, 4),
    /* RXB_DFE_TAP6:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1310, 11, 8),
    /* RXA_DFE_TAP6:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1284, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP8_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1366, 1, 0),
    /* RXD_DFE_TAP7_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1364, 3, 2),
    /* RXC_DFE_TAP8_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1340, 5, 4),
    /* RXC_DFE_TAP7_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1338, 7, 6),
    /* RXB_DFE_TAP8_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1314, 9, 8),
    /* RXB_DFE_TAP7_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1312, 11, 10),
    /* RXA_DFE_TAP8_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1288, 13, 12),
    /* RXA_DFE_TAP7_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1286, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP7:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1363, 3, 0),
    /* RXC_DFE_TAP7:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1337, 7, 4),
    /* RXB_DFE_TAP7:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1311, 11, 8),
    /* RXA_DFE_TAP7:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1285, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP8:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1365, 3, 0),
    /* RXC_DFE_TAP8:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1339, 7, 4),
    /* RXB_DFE_TAP8:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1313, 11, 8),
    /* RXA_DFE_TAP8:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1287, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP10_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1349, 1, 0),
    /* RXD_DFE_TAP9_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1368, 3, 2),
    /* RXC_DFE_TAP10_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1323, 5, 4),
    /* RXC_DFE_TAP9_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1342, 7, 6),
    /* RXB_DFE_TAP10_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1297, 9, 8),
    /* RXB_DFE_TAP9_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1316, 11, 10),
    /* RXA_DFE_TAP10_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1271, 13, 12),
    /* RXA_DFE_TAP9_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1290, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCD_GEN2r_fields[] =
{
    /* RXD_DFE_TAP9:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1367, 3, 0),
    /* RXC_DFE_TAP9:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1341, 7, 4),
    /* RXB_DFE_TAP9:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1315, 11, 8),
    /* RXA_DFE_TAP9:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1289, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFS_GEN2r_fields[] =
{
    /* RX_PF2_CTRL:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1406, 10, 8),
    /* RX_PF_CTRL:11:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1407, 14, 11)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SEL_GEN2r_fields[] =
{
    /* RX_LMS_THRESH_SEL:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1393, 7, 0),
    /* RX_PHASE_THRESH_SEL:8:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1408, 14, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_D_GEN2r_fields[] =
{
    /* RX_PI_CNT_BIN_D:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1409, 7, 0),
    /* RX_PI_CNT_BIN_DQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1410, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LD_GEN2r_fields[] =
{
    /* RX_PI_CNT_BIN_L_LD:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1415, 7, 0),
    /* RX_PI_CNT_BIN_D_LD:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1411, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_L_GEN2r_fields[] =
{
    /* RX_PI_CNT_BIN_L:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1413, 7, 0),
    /* RX_PI_CNT_BIN_LQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1414, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PD_GEN2r_fields[] =
{
    /* RX_PI_CNT_BIN_P_PD:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1418, 7, 0),
    /* RX_PI_CNT_BIN_D_PD:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1412, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_P_GEN2r_fields[] =
{
    /* RX_PI_CNT_BIN_P:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1416, 7, 0),
    /* RX_PI_CNT_BIN_PQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1417, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_RX_PI_CTL_GEN2r_fields[] =
{
    /* RX_PI_SLICERS_EN:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1423, 5, 0),
    /* RX_PI_PHASE_STEP_CNT:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1421, 8, 6),
    /* RX_PI_PHASE_STEP_DIR:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1422, 9, 9),
    /* RX_PI_MANUAL_MODE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1419, 10, 10),
    /* RX_PI_MANUAL_STROBE:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1420, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SCRATCH_GEN2r_fields[] =
{
    /* UC_DSC_SCRATCH:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1706, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_0_GEN2r_fields[] =
{
    /* EEE_MODE_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(754, 1, 1),
    /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(758, 2, 2),
    /* IGNORE_RX_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(872, 3, 3),
    /* CL72_TIMER_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(450, 4, 4),
    /* UC_TUNE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1709, 5, 5),
    /* HW_TUNE_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(860, 6, 6),
    /* EEE_MEASURE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(753, 8, 8),
    /* UC_ACK_DSC_EEE_DONE:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1698, 11, 11),
    /* UC_ACK_DSC_RESTART:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1699, 13, 13),
    /* UC_ACK_DSC_CONFIG:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1697, 14, 14),
    /* SET_MEAS_INCOMPLETE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1469, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_1_GEN2r_fields[] =
{
    /* RX_DSC_LOCK_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1390, 0, 0),
    /* RX_DSC_LOCK_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1391, 1, 1),
    /* DSC_CLR_FRC:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(738, 2, 2),
    /* DSC_CLR_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(739, 3, 3),
    /* TRNSUM_FRZ_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1554, 4, 4),
    /* TRNSUM_FRZ_FRC_VAL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1555, 5, 5),
    /* TIMER_DONE_FRC:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1531, 6, 6),
    /* TIMER_DONE_FRC_VAL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1532, 7, 7),
    /* FREQ_UPD_EN_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(840, 8, 8),
    /* FREQ_UPD_EN_FRC_VAL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(841, 9, 9),
    /* CDR_FRZ_FRC:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(405, 10, 10),
    /* CDR_FRZ_FRC_VAL:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(406, 11, 11),
    /* TRNSUM_CLR_FRC:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1544, 12, 12),
    /* TRNSUM_CLR_FRC_VAL:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1545, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_2_GEN2r_fields[] =
{
    /* EEE_LFSR_CNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(751, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_3_GEN2r_fields[] =
{
    /* MEASURE_LFSR_CNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(992, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_4_GEN2r_fields[] =
{
    /* ACQ_CDR_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(2, 4, 0),
    /* CDR_SETTLE_TIMEOUT:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(414, 9, 5),
    /* HW_TUNE_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(861, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_5_GEN2r_fields[] =
{
    /* MEASURE_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(993, 4, 0),
    /* EEE_ACQ_CDR_TIMEOUT:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(747, 9, 5),
    /* EEE_CDR_SETTLE_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(749, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_6_GEN2r_fields[] =
{
    /* EEE_HW_TUNE_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(750, 4, 0),
    /* EEE_ANA_PWR_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(748, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_7_GEN2r_fields[] =
{
    /* CDR_BWSEL_INTEG_ACQCDR:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(396, 3, 0),
    /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(397, 7, 4),
    /* CDR_BWSEL_INTEG_NORM:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(398, 11, 8),
    /* CDR_BWSEL_PROP_ACQCDR:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(399, 12, 12),
    /* CDR_BWSEL_PROP_NORM:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(401, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_8_GEN2r_fields[] =
{
    /* PHASE_ERR_OFFSET:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1132, 3, 0),
    /* EEE_PHASE_ERR_OFFSET:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(755, 7, 4),
    /* PHASE_ERR_OFFSET_EN:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1133, 9, 8),
    /* EEE_PHASE_ERR_OFFSET_EN:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(756, 11, 10),
    /* CDR_BWSEL_PROP_EEE_ACQCDR:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(400, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_CTL_9_GEN2r_fields[] =
{
    /* RX_RESTART_PMD:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1428, 0, 0),
    /* RX_RESTART_PMD_HOLD:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1429, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCK_GEN2r_fields[] =
{
    /* RX_DSC_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1389, 0, 0),
    /* MEAS_INCOMPLETE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(994, 1, 1),
    /* EEE_MEASURE_CNT:7:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(752, 15, 7)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOT_GEN2r_fields[] =
{
    /* DSC_STATE_EEE_ONE_HOT:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(744, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_GEN2r_fields[] =
{
    /* DSC_SM_SCRATCH:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(742, 3, 0),
    /* DSC_SM_READY_FOR_CMD:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(741, 4, 4),
    /* DSC_SM_GP_UC_REQ:5:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(740, 10, 5),
    /* DSC_STATE:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(743, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOT_GEN2r_fields[] =
{
    /* DSC_STATE_ONE_HOT:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(745, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_SM_STS_RESTART_GEN2r_fields[] =
{
    /* RESTART_PI_EXT_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1238, 0, 0),
    /* RESTART_SIGDET:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1240, 1, 1),
    /* RESTART_PMD_RESTART:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1239, 2, 2),
    /* EEE_QUIET_FROM_EEE_STATES:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(757, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_A_GEN2r_fields[] =
{
    /* TRNSUM_A:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1539, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOW_GEN2r_fields[] =
{
    /* TRNSUM_A_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1540, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_B_GEN2r_fields[] =
{
    /* TRNSUM_B:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1541, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOW_GEN2r_fields[] =
{
    /* TRNSUM_B_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1542, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_CTL_GEN2r_fields[] =
{
    /* TRNSUM_GAIN:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1556, 1, 0),
    /* TRNSUM_SEL_EMUX:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1564, 2, 2),
    /* TRNSUM_TAP_RANGE_SEL:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1566, 6, 4),
    /* TRNSUM_COR_SEL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1546, 9, 8),
    /* TRNSUM_QPHASE_MULT_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1562, 12, 12),
    /* TRNSUM_RANDOM_TAPSEL_DISABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1563, 13, 13),
    /* TRNSUM_EYE_CLOSURE_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1553, 14, 14),
    /* TRNSUM_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1551, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_C_GEN2r_fields[] =
{
    /* TRNSUM_C:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1543, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOW_GEN2r_fields[] =
{
    /* TRNSUM_C_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1547, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_D_GEN2r_fields[] =
{
    /* TRNSUM_D:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1548, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOW_GEN2r_fields[] =
{
    /* TRNSUM_D_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1549, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_GEN2r_fields[] =
{
    /* TRNSUM:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1538, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_LOW_GEN2r_fields[] =
{
    /* TRNSUM_LOW:6:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1558, 15, 6)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_MISC_GEN2r_fields[] =
{
    /* TDT_PRBS_SLIP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1520, 0, 0),
    /* CDR_1G_TRNSUM_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(395, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_1_GEN2r_fields[] =
{
    /* TRNSUM_PATTERN:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1559, 9, 0),
    /* TRNSUM_PATTERN_FULL_CHECK_OFF:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1561, 12, 12),
    /* TRNSUM_EDGE_PATTERN_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1550, 14, 14),
    /* TRNSUM_INV_PATTERN_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1557, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_2_GEN2r_fields[] =
{
    /* TRNSUM_PATTERN_BIT_EN:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1560, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTL_GEN2r_fields[] =
{
    /* TRNSUM_TAP_EN:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1565, 7, 0),
    /* TRNSUM_TAP_SIGN:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1567, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTL_GEN2r_fields[] =
{
    /* TDT_BIT_SEL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1516, 5, 0),
    /* TDT_PRBS_MODE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1519, 6, 6),
    /* TDT_TRNSUM_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1521, 7, 7),
    /* TDT_CYCLE_SEL:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1518, 11, 8),
    /* TDT_CYCLE_BIN:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1517, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_DSC_UC_CTL_GEN2r_fields[] =
{
    /* UC_DSC_GP_UC_REQ:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1704, 5, 0),
    /* UC_DSC_ERROR_FOUND:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1703, 6, 6),
    /* UC_DSC_READY_FOR_CMD:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1705, 7, 7),
    /* UC_DSC_SUPP_INFO:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1707, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_DSC_VGA_CTL_1_GEN2r_fields[] =
{
    /* VGA_TIMER_T2:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1729, 2, 0),
    /* UC_TRNSUM_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1708, 3, 3),
    /* DC_OFFS_WRITE_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(676, 4, 4),
    /* VGA_DEC:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1727, 5, 5),
    /* VGA_INC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1728, 7, 7),
    /* RX_VGA_CTRL_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1434, 14, 8),
    /* VGA_WRITE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1730, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_DSC_VGA_D_THR_STS_GEN2r_fields[] =
{
    /* RX_DATA_THRESH_SEL:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1388, 6, 0),
    /* RX_VGA_CTRL:8:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1433, 14, 8)
};
static uint32_t BCMI_TSCF_XGXS_ILKN_CTL0_GEN2r_fields[] =
{
    /* WM:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1734, 3, 0),
    /* ILKN_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(873, 4, 4),
    /* INV_TX_ORDER:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(884, 6, 6),
    /* INV_RX_ORDER:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(883, 7, 7),
    /* SOFT_RST_TX:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1489, 8, 8),
    /* SOFT_RST_RX:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1488, 9, 9),
    /* CREDIT_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(647, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_ILKN_STS0_GEN2r_fields[] =
{
    /* RXFIFO_EMPTY:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1374, 0, 0),
    /* RXFIFO_FULL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1375, 1, 1),
    /* RXFIFO_OVERRUN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1376, 2, 2),
    /* RXFIFO_UNDERRUN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1377, 3, 3),
    /* TXFIFO_EMPTY:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1589, 4, 4),
    /* TXFIFO_FULL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1590, 5, 5),
    /* TXFIFO_OVERRUN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1591, 6, 6),
    /* TXFIFO_UNDERRUN:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1592, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_GEN2r_fields[] =
{
    /* TIMEOUT_COUNT:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1529, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STS_GEN2r_fields[] =
{
    /* TIMEOUT_ERROR:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1530, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_DEVINPKG5_GEN2r_fields[] =
{
    /* CLAUSE22:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(598, 0, 0),
    /* PMA_PMD:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1161, 1, 1),
    /* WIS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1733, 2, 2),
    /* PCS_XS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1125, 3, 3),
    /* PHY_XS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1135, 4, 4),
    /* DTE_XS:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(746, 5, 5),
    /* TC:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1515, 6, 6),
    /* AN:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(222, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_LPBK_CTL_GEN2r_fields[] =
{
    /* LOCAL_PCS_LOOPBACK_ENABLE:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(942, 3, 0),
    /* REMOTE_PCS_LOOPBACK_ENABLE:4:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1228, 7, 4)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_MDIO_BCST_GEN2r_fields[] =
{
    /* MULTIPRTS_EN:7:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1071, 10, 7),
    /* PRTAD_BCST:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1207, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_SERDESID_GEN2r_fields[] =
{
    /* MODEL_NUMBER:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1058, 5, 0),
    /* TECH_PROC:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1522, 8, 6),
    /* BONDING:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(350, 10, 9),
    /* REV_NUMBER:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1257, 13, 11),
    /* REV_LETTER:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1256, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_SETUP_GEN2r_fields[] =
{
    /* TSC_CLK_CTRL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1568, 0, 0),
    /* CL73_VCO:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(467, 1, 1),
    /* STAND_ALONE_MODE:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1495, 2, 2),
    /* SINGLE_PORT_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1486, 3, 3),
    /* PORT_MODE_SEL:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1179, 6, 4),
    /* REFCLK_SEL:7:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1222, 9, 7),
    /* CL72_EN:10:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(448, 13, 10),
    /* MASTER_PORT_NUM:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(975, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_SPD_CTL_GEN2r_fields[] =
{
    /* PLL_RESET_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1155, 8, 8),
    /* TSC_CREDIT_SEL:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1569, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_GEN2r_fields[] =
{
    /* SYNCE_MODE_PHY_LANE0:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1507, 1, 0),
    /* SYNCE_MODE_PHY_LANE1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1508, 3, 2),
    /* SYNCE_MODE_PHY_LANE2:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1509, 5, 4),
    /* SYNCE_MODE_PHY_LANE3:6:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1510, 7, 6)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0_GEN2r_fields[] =
{
    /* SYNCE_STAGE0_MODE_PHY_LANE0:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1511, 1, 0),
    /* SYNCE_STAGE0_MODE_PHY_LANE1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1512, 3, 2),
    /* SYNCE_STAGE0_MODE_PHY_LANE2:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1513, 5, 4),
    /* SYNCE_STAGE0_MODE_PHY_LANE3:6:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1514, 7, 6)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_TICK_CTL_0_GEN2r_fields[] =
{
    /* TICK_DENOMINATOR:2:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1525, 11, 2),
    /* TICK_NUMERATOR_LOWER:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1526, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_MAIN0_TICK_CTL_1_GEN2r_fields[] =
{
    /* TICK_NUMERATOR_UPPER:0:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1527, 14, 0),
    /* TICK_OVERRIDE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1528, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_MDIO_AER_GEN2r_fields[] =
{
    /* MDIO_AER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(978, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDR_GEN2r_fields[] =
{
    /* MDIO_BRCST_PORT_ADDR:0:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(980, 4, 0)
};
static uint32_t BCMI_TSCF_XGXS_MDIO_BLK_ADDR_GEN2r_fields[] =
{
    /* MDIO_BLK_ADDR:4:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(979, 14, 4)
};
static uint32_t BCMI_TSCF_XGXS_MDIO_MASKDATA_GEN2r_fields[] =
{
    /* MDIO_MASKDATA:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(989, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_MDIO_MMD_SEL_GEN2r_fields[] =
{
    /* MDIO_DEV_CL22_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(983, 0, 0),
    /* MDIO_DEV_PMD_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(987, 2, 2),
    /* MDIO_DEV_AN_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(982, 3, 3),
    /* MDIO_DEV_PHY_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(986, 4, 4),
    /* MDIO_DEV_DTE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(984, 5, 5),
    /* MDIO_DEV_PCS_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(985, 6, 6),
    /* MDIO_MULTI_MMDS_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(990, 14, 14),
    /* MDIO_MULTI_PRTS_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(991, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_0_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1107, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_10_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_10:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1109, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_11_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_11:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1110, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_12_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_12:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1111, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_13_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_13:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1112, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_14_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_14:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1113, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_1_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1108, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_2_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1114, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_3_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1115, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_4_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1116, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_5_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_5:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1117, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_6_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_6:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1118, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_7_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_7:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1119, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_8_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_8:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1120, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PATT_GEN_SEQ_9_GEN2r_fields[] =
{
    /* PATT_GEN_SEQ_9:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1121, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PHYID2_GEN2r_fields[] =
{
    /* REGID1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1223, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PHYID3_GEN2r_fields[] =
{
    /* REGID2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1224, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_CRCERRCNT_GEN2r_fields[] =
{
    /* CRCERRCNT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(644, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL1_GEN2r_fields[] =
{
    /* TX_TEST_PORT_SEL:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1669, 1, 0),
    /* LPI_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(954, 2, 2),
    /* PRTP_DATA_PATTERN_SEL:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1208, 6, 3),
    /* RX_PORT_SEL:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1426, 8, 7),
    /* CLR_CRCCNT:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(604, 9, 9),
    /* RX_MSBUS_TYPE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1403, 10, 10),
    /* RX_PKT_CHECK_EN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1424, 11, 11),
    /* NUMBER_PKT:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1074, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL2_GEN2r_fields[] =
{
    /* IPG_SIZE:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(885, 4, 0),
    /* PKT_SIZE:5:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1138, 10, 5),
    /* PAYLOAD_TYPE:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1124, 13, 11),
    /* TX_MSBUS_TYPE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1627, 14, 14),
    /* PKTGEN_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1137, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_CTL3_GEN2r_fields[] =
{
    /* CLR_TXCNT:1:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(606, 4, 1),
    /* CLR_RXCNT:5:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(605, 8, 5)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK0_GEN2r_fields[] =
{
    /* ERROR_MASK_15_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(773, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK1_GEN2r_fields[] =
{
    /* ERROR_MASK_31_16:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(774, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK2_GEN2r_fields[] =
{
    /* ERROR_MASK_47_32:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(775, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK3_GEN2r_fields[] =
{
    /* ERROR_MASK_63_48:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(776, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERRMASK4_GEN2r_fields[] =
{
    /* ERROR_MASK_65_64:0:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(777, 1, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0_GEN2r_fields[] =
{
    /* ERRGEN_EN_PH0:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(765, 4, 0),
    /* ERRGEN_EN_PH1:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(766, 9, 5),
    /* ERRGEN_EN_PH2:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(767, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1_GEN2r_fields[] =
{
    /* ERRGEN_EN_PH3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(768, 4, 0),
    /* CL91_40B_ERRGEN_EN_P0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(486, 5, 5),
    /* CL91_40B_ERRGEN_EN_P1:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(487, 6, 6),
    /* CL91_40B_ERRGEN_EN_P2:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(488, 7, 7),
    /* CL91_40B_ERRGEN_EN_P3:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(489, 8, 8),
    /* CL91_80B_ERRGEN_EN_P0:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(490, 9, 9),
    /* CL91_80B_ERRGEN_EN_P1:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(491, 10, 10),
    /* CL91_80B_ERRGEN_EN_P2:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(492, 11, 11),
    /* CL91_80B_ERRGEN_EN_P3:12:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(493, 12, 12)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTES_GEN2r_fields[] =
{
    /* BYTE0:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(375, 7, 0),
    /* BYTE1:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(376, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0_GEN2r_fields[] =
{
    /* SEEDA0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1459, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1_GEN2r_fields[] =
{
    /* SEEDA1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1460, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2_GEN2r_fields[] =
{
    /* SEEDA2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1461, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3_GEN2r_fields[] =
{
    /* SEEDA3:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1462, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0_GEN2r_fields[] =
{
    /* SEEDB0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1463, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1_GEN2r_fields[] =
{
    /* SEEDB1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1464, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2_GEN2r_fields[] =
{
    /* SEEDB2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1465, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3_GEN2r_fields[] =
{
    /* SEEDB3:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1466, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_PKTGEN_PRTPCTL_GEN2r_fields[] =
{
    /* RX_PRTP_EN:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1427, 11, 8),
    /* TX_PRTP_EN:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1662, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_0_GEN2r_fields[] =
{
    /* VCO_STEP_TIME:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1726, 7, 0),
    /* VCO_START_TIME:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1725, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_1_GEN2r_fields[] =
{
    /* RETRY_TIME:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1242, 7, 0),
    /* PRE_FREQ_DET_TIME:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1206, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_2_GEN2r_fields[] =
{
    /* WIN_CAL_CNTR:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1732, 7, 0),
    /* RES_CAL_CNTR:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1241, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_3_GEN2r_fields[] =
{
    /* FAST_SEARCH_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(795, 0, 0),
    /* CAP_CNT_MASK_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(377, 1, 1),
    /* CAP_SEQ_CYA:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(389, 2, 2),
    /* CAP_RESTART:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(384, 3, 3),
    /* CAP_RETRY_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(385, 4, 4),
    /* CAP_FORCE_SLOWDOWN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(380, 5, 5),
    /* CAP_FORCE_SLOWDOWN_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(381, 6, 6),
    /* CAP_SELECT_M_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(388, 7, 7),
    /* CAP_SELECT_M:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(387, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_4_GEN2r_fields[] =
{
    /* PLL_LOCK_FRC_VAL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1148, 0, 0),
    /* PLL_LOCK_FRC:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1147, 1, 1),
    /* PLL_FORCE_CAP_PASS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1141, 2, 2),
    /* PLL_FORCE_CAP_PASS_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1142, 3, 3),
    /* PLL_FORCE_CAP_DONE:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1139, 4, 4),
    /* PLL_FORCE_CAP_DONE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1140, 5, 5),
    /* PLL_FORCE_FPASS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1145, 6, 6),
    /* PLL_FORCE_FDONE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1143, 7, 7),
    /* PLL_FORCE_FDONE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1144, 8, 8),
    /* VCO_RST_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1724, 9, 9),
    /* SLOWDN_XOR:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1487, 10, 10),
    /* FREQ_MONITOR_EN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(837, 11, 11),
    /* FREQ_DET_RESTART_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(833, 12, 12),
    /* FREQ_DET_RETRY_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(834, 13, 13),
    /* VCO_DONE_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1722, 14, 14),
    /* PLL_SEQ_START:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1160, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_5_GEN2r_fields[] =
{
    /* REFCLK_DIVCNT:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1220, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_6_GEN2r_fields[] =
{
    /* REFCLK_DIVCNT_SEL:0:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1221, 2, 0)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_7_GEN2r_fields[] =
{
    /* PLL_MODE:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1154, 3, 0),
    /* RESCAL_FRC_VAL:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1230, 7, 4),
    /* RESCAL_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1229, 8, 8),
    /* VCO_RANGE_ADJUST:9:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1723, 13, 9)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_0_GEN2r_fields[] =
{
    /* PLL_LOCK_LH_LL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1149, 0, 0),
    /* PLL_SEQ_PASS_LH_LL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1159, 1, 1),
    /* PLL_SEQ_DONE_LH_LL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1157, 2, 2),
    /* FREQ_PASS_SM_LH_LL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(839, 3, 3),
    /* FREQ_DONE_SM_LH_LL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(836, 4, 4),
    /* CAP_PASS_LH_LL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(383, 5, 5),
    /* CAP_DONE_LH_LL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(379, 6, 6),
    /* PLL_LOCK:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1146, 8, 8),
    /* PLL_SEQ_PASS:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1158, 9, 9),
    /* PLL_SEQ_DONE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1156, 10, 10),
    /* FREQ_PASS_SM:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(838, 11, 11),
    /* FREQ_DONE_SM:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(835, 12, 12),
    /* CAP_PASS:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(382, 13, 13),
    /* CAP_DONE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(378, 14, 14),
    /* LOST_PLL_LOCK_SM:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(951, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_1_GEN2r_fields[] =
{
    /* CAP_SELECT:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(386, 7, 0),
    /* RESCAL_IN:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1231, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBG_GEN2r_fields[] =
{
    /* DBG_SLOWDN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(667, 0, 0),
    /* DBG_SLOWDN_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(668, 1, 1),
    /* DBG_FDBCK:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(664, 2, 2),
    /* DBG_CAP_STATE_ONE_HOT:3:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(651, 7, 3),
    /* DBG_PLL_STATE_ONE_HOT:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(666, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X1_CTL_GEN2r_fields[] =
{
    /* CORE_DP_H_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(619, 0, 0),
    /* POR_H_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1180, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X1_MODE_GEN2r_fields[] =
{
    /* CORE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(623, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X1_OVRR_GEN2r_fields[] =
{
    /* PLL_LOCK_OVRD:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1150, 0, 0),
    /* CORE_MODE_OEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(624, 2, 2),
    /* CORE_DP_H_RSTB_OEN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(620, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X1_STS_GEN2r_fields[] =
{
    /* PLL_LOCK_STS:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1151, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_CTL_GEN2r_fields[] =
{
    /* LN_DP_H_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(924, 0, 0),
    /* LN_H_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(927, 1, 1),
    /* LN_TX_H_PWRDN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(937, 2, 2),
    /* LN_RX_H_PWRDN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(929, 3, 3),
    /* TX_DISABLE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1613, 8, 8),
    /* OSR_MODE:9:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1093, 12, 9)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_EEE_CTL_GEN2r_fields[] =
{
    /* TX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1626, 1, 0),
    /* RX_MODE:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1399, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_EEE_STS_GEN2r_fields[] =
{
    /* ENERGY_DETECT:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(760, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_LATCH_STS_GEN2r_fields[] =
{
    /* RX_LOCK_LL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1396, 0, 0),
    /* RX_LOCK_LH:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1394, 1, 1),
    /* SIGNAL_DETECT_LL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1480, 2, 2),
    /* SIGNAL_DETECT_LH:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1478, 3, 3),
    /* RX_CLK_VLD_LL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1383, 4, 4),
    /* RX_CLK_VLD_LH:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1381, 5, 5),
    /* RX_LOCK_LIVE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1395, 8, 8),
    /* SIGNAL_DETECT_LIVE:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1479, 9, 9),
    /* RX_CLK_VLD_LIVE:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1382, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_MODE_GEN2r_fields[] =
{
    /* LANE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(900, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_OVRR_GEN2r_fields[] =
{
    /* RX_LOCK_OVRD:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1397, 0, 0),
    /* SIGNAL_DETECT_OVRD:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1481, 1, 1),
    /* RX_CLK_VLD_OVRD:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1384, 2, 2),
    /* LANE_MODE_OEN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(901, 3, 3),
    /* OSR_MODE_OEN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1096, 4, 4),
    /* TX_DISABLE_OEN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1614, 5, 5),
    /* LN_DP_H_RSTB_OEN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(925, 6, 6),
    /* TX_CLK_VLD_OVRD:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1611, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_PMD_X4_STS_GEN2r_fields[] =
{
    /* RX_LOCK_STS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1398, 0, 0),
    /* SIGNAL_DETECT_STS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1484, 1, 1),
    /* RX_CLK_VLD_STS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1385, 2, 2),
    /* TX_CLK_VLD_STS:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1612, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_CL91_CFG_GEN2r_fields[] =
{
    /* SET_SYMB_ERR_WINDOW_128:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1470, 1, 1),
    /* FEC_BYP_CORR_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(800, 2, 2),
    /* FEC_BYP_IND_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(802, 3, 3),
    /* FEC_DBG_BYP_CORR:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(803, 4, 4),
    /* CL91_AM_SPACING_1024:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(497, 5, 5),
    /* CL91_FC_LOCK_CORR_CW:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(518, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_DEC_CTL_1_GEN2r_fields[] =
{
    /* CL49_BER_LIMIT:2:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(431, 7, 2),
    /* CL82_BER_LIMIT:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(473, 14, 8),
    /* SET_BER_WINDOW_512:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1468, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_0_GEN2r_fields[] =
{
    /* CL82_DSWIN:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(475, 5, 0),
    /* CL82_DSWIN_100G:6:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(476, 10, 6)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_1_GEN2r_fields[] =
{
    /* CL82_DSWIN_CL91:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(477, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPT_0_GEN2r_fields[] =
{
    /* CORRUPT_ECC_FEC_MEM_0:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(640, 1, 0),
    /* CORRUPT_ECC_FEC_MEM_1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(641, 3, 2),
    /* CORRUPT_ECC_FEC_MEM_2:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(642, 5, 4),
    /* CORRUPT_ECC_FEC_MEM_3:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(643, 7, 6),
    /* CORRUPT_ECC_CL91_FEC_RAM1_LO:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(634, 9, 8),
    /* CORRUPT_ECC_CL91_FEC_RAM1_HI:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(633, 11, 10),
    /* CORRUPT_ECC_CL91_FEC_RAM2_LO:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(636, 13, 12),
    /* CORRUPT_ECC_CL91_FEC_RAM2_HI:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(635, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEM_GEN2r_fields[] =
{
    /* DISABLE_ECC_FEC_MEM_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(726, 0, 0),
    /* DISABLE_ECC_FEC_MEM_1:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(727, 1, 1),
    /* DISABLE_ECC_FEC_MEM_2:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(728, 2, 2),
    /* DISABLE_ECC_FEC_MEM_3:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(729, 3, 3),
    /* DISABLE_ECC_CL91_FEC_RAM1_LO:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(720, 4, 4),
    /* DISABLE_ECC_CL91_FEC_RAM1_HI:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(719, 5, 5),
    /* DISABLE_ECC_CL91_FEC_RAM2_LO:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(722, 6, 6),
    /* DISABLE_ECC_CL91_FEC_RAM2_HI:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(721, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BIT_GEN2r_fields[] =
{
    /* FEC_MEM_0_1BIT_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(807, 0, 0),
    /* FEC_MEM_1_1BIT_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(811, 1, 1),
    /* FEC_MEM_2_1BIT_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(815, 2, 2),
    /* FEC_MEM_3_1BIT_INT_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(819, 3, 3),
    /* CL91_FEC_RAM1_LO_1BIT_INT_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(535, 4, 4),
    /* CL91_FEC_RAM1_HI_1BIT_INT_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(531, 5, 5),
    /* CL91_FEC_RAM2_LO_1BIT_INT_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(543, 6, 6),
    /* CL91_FEC_RAM2_HI_1BIT_INT_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(539, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BIT_GEN2r_fields[] =
{
    /* FEC_MEM_0_2BIT_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(809, 0, 0),
    /* FEC_MEM_1_2BIT_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(813, 1, 1),
    /* FEC_MEM_2_2BIT_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(817, 2, 2),
    /* FEC_MEM_3_2BIT_INT_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(821, 3, 3),
    /* CL91_FEC_RAM1_LO_2BIT_INT_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(537, 4, 4),
    /* CL91_FEC_RAM1_HI_2BIT_INT_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(533, 5, 5),
    /* CL91_FEC_RAM2_LO_2BIT_INT_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(545, 6, 6),
    /* CL91_FEC_RAM2_HI_2BIT_INT_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(541, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BIT_GEN2r_fields[] =
{
    /* FEC_MEM_0_1BIT_INT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(808, 0, 0),
    /* FEC_MEM_1_1BIT_INT_STATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(812, 1, 1),
    /* FEC_MEM_2_1BIT_INT_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(816, 2, 2),
    /* FEC_MEM_3_1BIT_INT_STATUS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(820, 3, 3),
    /* CL91_FEC_RAM1_LO_1BIT_INT_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(536, 4, 4),
    /* CL91_FEC_RAM1_HI_1BIT_INT_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(532, 5, 5),
    /* CL91_FEC_RAM2_LO_1BIT_INT_STATUS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(544, 6, 6),
    /* CL91_FEC_RAM2_HI_1BIT_INT_STATUS:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(540, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BIT_GEN2r_fields[] =
{
    /* FEC_MEM_0_2BIT_INT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(810, 0, 0),
    /* FEC_MEM_1_2BIT_INT_STATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(814, 1, 1),
    /* FEC_MEM_2_2BIT_INT_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(818, 2, 2),
    /* FEC_MEM_3_2BIT_INT_STATUS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(822, 3, 3),
    /* CL91_FEC_RAM1_LO_2BIT_INT_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(538, 4, 4),
    /* CL91_FEC_RAM1_HI_2BIT_INT_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(534, 5, 5),
    /* CL91_FEC_RAM2_LO_2BIT_INT_STATUS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(546, 6, 6),
    /* CL91_FEC_RAM2_HI_2BIT_INT_STATUS:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(542, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_0_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_FEC_0:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(789, 13, 0),
    /* ONE_BIT_ERR_EVENT_FEC_0:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1089, 14, 14),
    /* TWO_BIT_ERR_EVENT_FEC_0:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1580, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_1_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_FEC_1:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(790, 13, 0),
    /* ONE_BIT_ERR_EVENT_FEC_1:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1090, 14, 14),
    /* TWO_BIT_ERR_EVENT_FEC_1:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1581, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_2_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_FEC_2:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(791, 13, 0),
    /* ONE_BIT_ERR_EVENT_FEC_2:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1091, 14, 14),
    /* TWO_BIT_ERR_EVENT_FEC_2:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1582, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_3_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_FEC_3:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(792, 13, 0),
    /* ONE_BIT_ERR_EVENT_FEC_3:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1092, 14, 14),
    /* TWO_BIT_ERR_EVENT_FEC_3:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1583, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_RF_MEM_CTL_GEN2r_fields[] =
{
    /* RF_MEM_TM:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1258, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_fields[] =
{
    /* LOGICAL0_TO_PHY_SEL:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(943, 1, 0),
    /* LOGICAL1_TO_PHY_SEL:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(944, 3, 2),
    /* LOGICAL2_TO_PHY_SEL:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(945, 5, 4),
    /* LOGICAL3_TO_PHY_SEL:6:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(946, 7, 6)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_SRF_MEM_CTL_GEN2r_fields[] =
{
    /* SRF_MEM_TM:0:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1494, 11, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_HI_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(782, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1082, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1573, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_LO_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(783, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1083, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1574, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_HI_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(784, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1084, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1575, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_LO_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(785, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1085, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1576, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X2_CL82_SCRIDLE_TEST_ERR_GEN2r_fields[] =
{
    /* CL82_SCRIDLE_TEST_ERR:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(482, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X2_MISC_0_GEN2r_fields[] =
{
    /* BYPASS_CL82RXSM:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(374, 0, 0),
    /* DIS_CL82_BERMON:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(731, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_RX_X2_MISC_1_GEN2r_fields[] =
{
    /* CL82_RX_RF_ENABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(481, 0, 0),
    /* CL82_RX_LF_ENABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(479, 1, 1),
    /* CL82_RX_LI_ENABLE:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(480, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STS_GEN2r_fields[] =
{
    /* AM_LOCK_LL_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(209, 0, 0),
    /* AM_LOCK_LH_0:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(204, 1, 1),
    /* AM_LOCK_LL_1:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(210, 2, 2),
    /* AM_LOCK_LH_1:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(205, 3, 3),
    /* AM_LOCK_LL_2:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(211, 4, 4),
    /* AM_LOCK_LH_2:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(206, 5, 5),
    /* AM_LOCK_LL_3:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(212, 6, 6),
    /* AM_LOCK_LH_3:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(207, 7, 7),
    /* AM_LOCK_LL_4:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(213, 8, 8),
    /* AM_LOCK_LH_4:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(208, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT_0_GEN2r_fields[] =
{
    /* BIP_ERROR_COUNT_0:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(328, 7, 0),
    /* BIP_ERROR_COUNT_1:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(329, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT_1_GEN2r_fields[] =
{
    /* BIP_ERROR_COUNT_2:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(330, 7, 0),
    /* BIP_ERROR_COUNT_3:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(331, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BIPCNT_2_GEN2r_fields[] =
{
    /* BIP_ERROR_COUNT_4:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(332, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFG_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* BLK_LOCK_ON_CTRL:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(333, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0_GEN2r_fields[] =
{
    /* LANE0_DEBUG_INFO:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(886, 7, 0),
    /* LANE1_DEBUG_INFO:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(887, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1_GEN2r_fields[] =
{
    /* LANE2_DEBUG_INFO:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(888, 7, 0),
    /* LANE3_DEBUG_INFO:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(889, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2_GEN2r_fields[] =
{
    /* LANE4_DEBUG_INFO:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(890, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STS_GEN2r_fields[] =
{
    /* BS_STATUS:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(359, 4, 0),
    /* BS_PMD_LOCK:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(356, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STS_GEN2r_fields[] =
{
    /* BLOCK_LOCK_LL_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(344, 0, 0),
    /* BLOCK_LOCK_LH_0:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(339, 1, 1),
    /* BLOCK_LOCK_LL_1:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(345, 2, 2),
    /* BLOCK_LOCK_LH_1:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(340, 3, 3),
    /* BLOCK_LOCK_LL_2:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(346, 4, 4),
    /* BLOCK_LOCK_LH_2:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(341, 5, 5),
    /* BLOCK_LOCK_LL_3:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(347, 6, 6),
    /* BLOCK_LOCK_LH_3:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(342, 7, 7),
    /* BLOCK_LOCK_LL_4:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(348, 8, 8),
    /* BLOCK_LOCK_LH_4:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(343, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_BERCNT_GEN2r_fields[] =
{
    /* CL36RX_BER_COUNT_PER_LN:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(417, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_CTL_GEN2r_fields[] =
{
    /* CL36RX_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 0, 0),
    /* CL36RX_LPI_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(423, 1, 1),
    /* CL36RX_DISABLE_CARRIER_EXTEND:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(419, 2, 2),
    /* CL36RX_FORCE_COMMA_ALIGN_ENABLE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(422, 3, 3),
    /* CL36RX_BER_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(418, 4, 4)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_0_GEN2r_fields[] =
{
    /* CL36RX_SYNCACQ_STATE_CODED_PER_LN:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(425, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_1_GEN2r_fields[] =
{
    /* CL36RX_SYNCACQ_HIS_STATE_PER_LN:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(424, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL49_SCRIDLE_TEST_ERR_GEN2r_fields[] =
{
    /* CL49_SCRIDLE_TEST_ERR:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(440, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_0_GEN2r_fields[] =
{
    /* AM_LOCK_HIS_STATE_PSLL_0:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(199, 9, 0),
    /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(20, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_1_GEN2r_fields[] =
{
    /* AM_LOCK_HIS_STATE_PSLL_1:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(200, 9, 0),
    /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(21, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_2_GEN2r_fields[] =
{
    /* AM_LOCK_HIS_STATE_PSLL_2:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(201, 9, 0),
    /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(22, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_3_GEN2r_fields[] =
{
    /* AM_LOCK_HIS_STATE_PSLL_3:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(202, 9, 0),
    /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(23, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_4_GEN2r_fields[] =
{
    /* AM_LOCK_HIS_STATE_PSLL_4:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(203, 9, 0),
    /* AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(24, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_0_GEN2r_fields[] =
{
    /* AM_LOCK_STATE_PSLL_0:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(214, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_1_GEN2r_fields[] =
{
    /* AM_LOCK_STATE_PSLL_1:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(215, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_2_GEN2r_fields[] =
{
    /* AM_LOCK_STATE_PSLL_2:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(216, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_3_GEN2r_fields[] =
{
    /* AM_LOCK_STATE_PSLL_3:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(217, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_4_GEN2r_fields[] =
{
    /* AM_LOCK_STATE_PSLL_4:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(218, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FC_SLIP_CNT_GEN2r_fields[] =
{
    /* CL91_FC_SLIP_CNT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FC_STS_GEN2r_fields[] =
{
    /* CL91_FC_SYNC_LIVE_STATE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(521, 1, 0),
    /* CL91_FC_SYNC_LATCHED_STATE:2:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(520, 5, 2),
    /* CL91_FC_CW_SYNC_LIVE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(516, 6, 6),
    /* CL91_FC_CW_SYNC_LL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(517, 7, 7),
    /* CL91_FC_CW_SYNC_LH:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(515, 8, 8),
    /* CL91_FC_CW_GOOD_CNT:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(514, 10, 9),
    /* CL91_FC_CW_BAD_CNT:11:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(513, 12, 11)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_0_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_LOWER_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_1_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_LOWER_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(825, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_2_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_LOWER_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(826, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_3_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_LOWER_3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(827, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_0_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_UPPER_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(828, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_1_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_UPPER_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(829, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_2_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_UPPER_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(830, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_3_GEN2r_fields[] =
{
    /* FEC_SYMBOL_ERROR_COUNTER_UPPER_3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_RXP_STS_GEN2r_fields[] =
{
    /* RESTART_LOCK_LIVE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1236, 0, 0),
    /* RESTART_LOCK_LL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1237, 1, 1),
    /* RESTART_LOCK_LH:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1235, 2, 2),
    /* FEC_ALIGN_STATUS_LIVE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(797, 3, 3),
    /* FEC_ALIGN_STATUS_LL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(798, 4, 4),
    /* FEC_ALIGN_STATUS_LH:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(796, 5, 5),
    /* HI_SER_LIVE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(855, 6, 6),
    /* HI_SER_LL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(856, 7, 7),
    /* HI_SER_LH:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(854, 8, 8),
    /* FEC_BYP_CORR_ABILITY:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(799, 9, 9),
    /* FEC_BYP_IND_ABILITY:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(801, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_RX_CTL_0_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(512, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(832, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* FEC_BYP_CORR_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(800, 13, 13),
    /* FEC_BYP_IND_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(802, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STS_GEN2r_fields[] =
{
    /* CL91_AMPS_LOCK_LIVE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(495, 0, 0),
    /* CL91_AMPS_LOCK_LL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(496, 1, 1),
    /* CL91_AMPS_LOCK_LH:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(494, 2, 2),
    /* CL91_FEC_LANE_MAP:3:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(528, 4, 3),
    /* CL91_FEC_LANE_MAP_VALID:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(529, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_THR_GEN2r_fields[] =
{
    /* SYMBOL_ERR_CNT_THRESHOLD:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1505, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_CL91_TMR_GEN2r_fields[] =
{
    /* SYMBOL_ERROR_TMR_PERIOD:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1504, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_CTL_0_GEN2r_fields[] =
{
    /* CL49_RX_RF_ENABLE:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(438, 4, 4),
    /* CL49_RX_LF_ENABLE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(436, 5, 5),
    /* CL49_RX_LI_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(437, 6, 6),
    /* DIS_SCRAMBLER:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(732, 7, 7),
    /* DISABLE_CL49_BERMON:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(715, 8, 8),
    /* HG2_CODEC:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(847, 9, 9),
    /* HG2_ENABLE:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(848, 12, 12),
    /* HG2_MESSAGE_INVALID_CODE_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(849, 13, 13),
    /* R_TEST_MODE_CFG:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1451, 14, 14),
    /* BYPASS_CL49RXSM:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(373, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS_0_GEN2r_fields[] =
{
    /* BERMON_CURRENT_STATE:0:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(322, 4, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS_1_GEN2r_fields[] =
{
    /* BERMON_HISTORY_STATE:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(323, 4, 0),
    /* CL49_RXSM_HISTORY_STATE:5:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(435, 12, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS_2_GEN2r_fields[] =
{
    /* CL49_RXSM_CURRENT_STATE:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(434, 7, 0),
    /* CL49_R_TYPE_CODED:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(439, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_DEC_STS_3_GEN2r_fields[] =
{
    /* IEEE_ERRORED_BLOCKS:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(868, 7, 0),
    /* CL49_BER_COUNT:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(430, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_CORRUPT_GEN2r_fields[] =
{
    /* CORRUPT_ECC_CL91_BUFFER_BLK0:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(630, 1, 0),
    /* CORRUPT_ECC_CL91_BUFFER_BLK1:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(631, 3, 2),
    /* CORRUPT_ECC_CL91_BUFFER_BLK2:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(632, 5, 4),
    /* CORRUPT_ECC_DESKEW_MEM_0:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(637, 7, 6),
    /* CORRUPT_ECC_DESKEW_MEM_1:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(638, 9, 8),
    /* CORRUPT_ECC_DESKEW_MEM_2:10:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(639, 11, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_DIS_ECC_MEM_GEN2r_fields[] =
{
    /* DISABLE_ECC_CL91_BUFFER_BLK0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(716, 0, 0),
    /* DISABLE_ECC_CL91_BUFFER_BLK1:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(717, 1, 1),
    /* DISABLE_ECC_CL91_BUFFER_BLK2:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(718, 2, 2),
    /* DISABLE_ECC_DESKEW_MEM_0:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(723, 3, 3),
    /* DISABLE_ECC_DESKEW_MEM_1:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(724, 4, 4),
    /* DISABLE_ECC_DESKEW_MEM_2:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(725, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_1BIT_GEN2r_fields[] =
{
    /* CL91_BUFFER_BLK0_1BIT_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(500, 0, 0),
    /* CL91_BUFFER_BLK1_1BIT_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(504, 1, 1),
    /* CL91_BUFFER_BLK2_1BIT_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(508, 2, 2),
    /* DESKEW_MEM_0_1BIT_INT_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(692, 3, 3),
    /* DESKEW_MEM_1_1BIT_INT_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(696, 4, 4),
    /* DESKEW_MEM_2_1BIT_INT_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(700, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_2BIT_GEN2r_fields[] =
{
    /* CL91_BUFFER_BLK0_2BIT_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(502, 0, 0),
    /* CL91_BUFFER_BLK1_2BIT_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(506, 1, 1),
    /* CL91_BUFFER_BLK2_2BIT_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(510, 2, 2),
    /* DESKEW_MEM_0_2BIT_INT_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(694, 3, 3),
    /* DESKEW_MEM_1_2BIT_INT_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(698, 4, 4),
    /* DESKEW_MEM_2_2BIT_INT_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(702, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_1BIT_GEN2r_fields[] =
{
    /* CL91_BUFFER_BLK0_1BIT_INT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(501, 0, 0),
    /* CL91_BUFFER_BLK1_1BIT_INT_STATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(505, 1, 1),
    /* CL91_BUFFER_BLK2_1BIT_INT_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(509, 2, 2),
    /* DESKEW_MEM_0_1BIT_INT_STATUS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(693, 3, 3),
    /* DESKEW_MEM_1_1BIT_INT_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(697, 4, 4),
    /* DESKEW_MEM_2_1BIT_INT_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(701, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_2BIT_GEN2r_fields[] =
{
    /* CL91_BUFFER_BLK0_2BIT_INT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(503, 0, 0),
    /* CL91_BUFFER_BLK1_2BIT_INT_STATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(507, 1, 1),
    /* CL91_BUFFER_BLK2_2BIT_INT_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(511, 2, 2),
    /* DESKEW_MEM_0_2BIT_INT_STATUS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(695, 3, 3),
    /* DESKEW_MEM_1_2BIT_INT_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(699, 4, 4),
    /* DESKEW_MEM_2_2BIT_INT_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(703, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(779, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1079, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1570, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(780, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1080, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1571, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(781, 13, 0),
    /* ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1081, 14, 14),
    /* TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1572, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_DESKEW_0:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(786, 13, 0),
    /* ONE_BIT_ERR_EVENT_DESKEW_0:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1086, 14, 14),
    /* TWO_BIT_ERR_EVENT_DESKEW_0:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1577, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_DESKEW_1:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(787, 13, 0),
    /* ONE_BIT_ERR_EVENT_DESKEW_1:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1087, 14, 14),
    /* TWO_BIT_ERR_EVENT_DESKEW_1:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1578, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_fields[] =
{
    /* ERR_EVENT_ADDRESS_DESKEW_2:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(788, 13, 0),
    /* ONE_BIT_ERR_EVENT_DESKEW_2:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1088, 14, 14),
    /* TWO_BIT_ERR_EVENT_DESKEW_2:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1579, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_0_GEN2r_fields[] =
{
    /* DBG_ERR_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(663, 0, 0),
    /* BURST_ERR_STATUS_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(372, 1, 1),
    /* DEC_MAX_PM:2:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(685, 7, 2),
    /* INVALID_PARITY_CNT:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(882, 11, 8),
    /* GOOD_PARITY_CNT:12:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(842, 14, 12)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_1_GEN2r_fields[] =
{
    /* DEC_GAP_COUNT_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(684, 1, 1),
    /* DEC_17B_BURST_GAP_COUNT:2:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(679, 4, 2),
    /* DEC_18B_BURST_GAP_COUNT:5:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(680, 7, 5),
    /* DEC_19B_BURST_GAP_COUNT:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(681, 10, 8),
    /* DEC_PM_MODE:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(686, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_2_GEN2r_fields[] =
{
    /* FEC_ERROR_CODE_ALL_PER_STREAM:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(805, 4, 0),
    /* DBG_ENABLE_PER_STREAM:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(652, 9, 5),
    /* FEC_ERR_ENABLE_PER_STREAM:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(806, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_3_GEN2r_fields[] =
{
    /* ERROR_EN_OVR_PER_STREAM:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(771, 4, 0),
    /* ERROR_EN_OVR_VAL_PER_STREAM:5:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(772, 9, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_ALGN_FSM_ST_GEN2r_fields[] =
{
    /* CL91_FEC_ALGN_FSM_LIVE_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(523, 2, 0),
    /* CL91_FEC_ALGN_FSM_LATCHED_STATE:3:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(522, 9, 3)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_0_GEN2r_fields[] =
{
    /* CL91_FEC_CORR_BIT_CNTR_LOWER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(524, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_1_GEN2r_fields[] =
{
    /* CL91_FEC_CORR_BIT_CNTR_UPPER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(525, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_0_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSH_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(362, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_1_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSH_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(363, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_2_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSH_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(364, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_3_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSH_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(365, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_4_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSH_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(366, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_0_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSL_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(367, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_1_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSL_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(368, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_2_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSL_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(369, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_3_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSL_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(370, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_4_GEN2r_fields[] =
{
    /* BURST_ERR_STATUSL_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(371, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_0_GEN2r_fields[] =
{
    /* CORCOUNTH_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(609, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_1_GEN2r_fields[] =
{
    /* CORCOUNTH_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(610, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_2_GEN2r_fields[] =
{
    /* CORCOUNTH_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(611, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_3_GEN2r_fields[] =
{
    /* CORCOUNTH_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(612, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_4_GEN2r_fields[] =
{
    /* CORCOUNTH_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(613, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_0_GEN2r_fields[] =
{
    /* CORCOUNTL_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(614, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_1_GEN2r_fields[] =
{
    /* CORCOUNTL_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(615, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_2_GEN2r_fields[] =
{
    /* CORCOUNTL_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(616, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_3_GEN2r_fields[] =
{
    /* CORCOUNTL_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(617, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_4_GEN2r_fields[] =
{
    /* CORCOUNTL_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(618, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_0_GEN2r_fields[] =
{
    /* CL91_FEC_CORR_CW_CNTR_LOWER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(526, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_1_GEN2r_fields[] =
{
    /* CL91_FEC_CORR_CW_CNTR_UPPER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(527, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_0_GEN2r_fields[] =
{
    /* DBG_ERRH_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(653, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_1_GEN2r_fields[] =
{
    /* DBG_ERRH_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(654, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_2_GEN2r_fields[] =
{
    /* DBG_ERRH_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(655, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_3_GEN2r_fields[] =
{
    /* DBG_ERRH_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(656, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_4_GEN2r_fields[] =
{
    /* DBG_ERRH_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_0_GEN2r_fields[] =
{
    /* DBG_ERRL_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(658, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_1_GEN2r_fields[] =
{
    /* DBG_ERRL_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(659, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_2_GEN2r_fields[] =
{
    /* DBG_ERRL_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(660, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_3_GEN2r_fields[] =
{
    /* DBG_ERRL_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(661, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_4_GEN2r_fields[] =
{
    /* DBG_ERRL_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(662, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_ST_GEN2r_fields[] =
{
    /* CL91_FEC_SYNC_FSM_LIVE_STATE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(548, 1, 0),
    /* CL91_FEC_SYNC_FSM_LATCHED_STATE:2:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(547, 5, 2)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_0_GEN2r_fields[] =
{
    /* UNCORCOUNTH_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1710, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_1_GEN2r_fields[] =
{
    /* UNCORCOUNTH_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1711, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_2_GEN2r_fields[] =
{
    /* UNCORCOUNTH_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1712, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_3_GEN2r_fields[] =
{
    /* UNCORCOUNTH_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1713, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_4_GEN2r_fields[] =
{
    /* UNCORCOUNTH_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1714, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_0_GEN2r_fields[] =
{
    /* UNCORCOUNTL_STREAM0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1715, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_1_GEN2r_fields[] =
{
    /* UNCORCOUNTL_STREAM1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1716, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_2_GEN2r_fields[] =
{
    /* UNCORCOUNTL_STREAM2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1717, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_3_GEN2r_fields[] =
{
    /* UNCORCOUNTL_STREAM3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1718, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_4_GEN2r_fields[] =
{
    /* UNCORCOUNTL_STREAM4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1719, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_0_GEN2r_fields[] =
{
    /* CL91_FEC_UNCORR_CW_CNTR_LOWER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(549, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_1_GEN2r_fields[] =
{
    /* CL91_FEC_UNCORR_CW_CNTR_UPPER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(550, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r_fields[] =
{
    /* MSA_IEEE_DET_TIMEPERIOD:0:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1069, 12, 0),
    /* MSA_IEEE_DET_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1067, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_STS_GEN2r_fields[] =
{
    /* MSA_IEEE_DET_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1068, 2, 0),
    /* RESOLVED_25_MODE:3:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1233, 4, 3)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_LNK_CTL_GEN2r_fields[] =
{
    /* LATCH_LINKDOWN_ENABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(906, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_CTL_0_GEN2r_fields[] =
{
    /* LPI_ENABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(955, 0, 0),
    /* FEC_ENABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(804, 1, 1),
    /* CL91_FEC_MODE:2:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(530, 4, 2),
    /* BLOCK_NON_FC_BLK_TYPES:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(349, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS_1_GEN2r_fields[] =
{
    /* DESKEW_STATUS_LL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(709, 0, 0),
    /* DESKEW_STATUS_LH:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(708, 1, 1),
    /* LINK_STATUS_LL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(923, 2, 2),
    /* LINK_STATUS_LH:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(922, 3, 3),
    /* HI_BER_LL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(853, 4, 4),
    /* HI_BER_LH:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(852, 5, 5),
    /* LPI_RECEIVED_LH:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(957, 6, 6),
    /* LINK_INTERRUPT_LH:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(920, 7, 7),
    /* REMOTE_FAULT_LH:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1226, 8, 8),
    /* LOCAL_FAULT_LH:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(941, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_0_GEN2r_fields[] =
{
    /* AM_LOCK_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(194, 0, 0),
    /* AM_LOCK_1:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(195, 1, 1),
    /* AM_LOCK_2:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(196, 2, 2),
    /* AM_LOCK_3:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(197, 3, 3),
    /* AM_LOCK_4:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(198, 4, 4),
    /* BLOCK_LOCK_0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(334, 5, 5),
    /* BLOCK_LOCK_1:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(335, 6, 6),
    /* BLOCK_LOCK_2:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(336, 7, 7),
    /* BLOCK_LOCK_3:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(337, 8, 8),
    /* BLOCK_LOCK_4:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(338, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_1_GEN2r_fields[] =
{
    /* DESKEW_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(707, 0, 0),
    /* LINK_STATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(921, 1, 1),
    /* HI_BER:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(851, 2, 2),
    /* LPI_RECEIVED:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(956, 3, 3),
    /* LINK_INTERRUPT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(919, 4, 4),
    /* REMOTE_FAULT:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1225, 5, 5),
    /* LOCAL_FAULT:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(940, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PMA_CTL_0_GEN2r_fields[] =
{
    /* RSTB_LANE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1264, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PRTPERRCTR_GEN2r_fields[] =
{
    /* PRTP_ERR_COUNT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1209, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PRTPSTS_GEN2r_fields[] =
{
    /* PRTP_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1210, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_0_GEN2r_fields[] =
{
    /* PSLL0_TO_VL_MAPPING:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1211, 4, 0),
    /* PSLL1_TO_VL_MAPPING:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1212, 9, 5),
    /* PSLL2_TO_VL_MAPPING:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1213, 14, 10)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_1_GEN2r_fields[] =
{
    /* PSLL3_TO_VL_MAPPING:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1214, 4, 0),
    /* PSLL4_TO_VL_MAPPING:5:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1215, 9, 5)
};
static uint32_t BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIV_GEN2r_fields[] =
{
    /* SYNCE_FRACTIONAL_DIVSOR_CFG:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1506, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNT_GEN2r_fields[] =
{
    /* PIPELINE_RESET_COUNT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1136, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMR_GEN2r_fields[] =
{
    /* PLL_LOCK_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1153, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMR_GEN2r_fields[] =
{
    /* PMD_LOCK_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1170, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0_GEN2r_fields[] =
{
    /* SCR_MODE:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1453, 3, 1),
    /* T_PMA_BTMX_MODE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 5, 4),
    /* T_HG2_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1680, 6, 6),
    /* T_ENC_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 8, 7),
    /* T_FIFO_MODE:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 10, 9),
    /* OS_MODE:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 14, 11),
    /* CL72_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_6_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1670, 0, 0),
    /* T_FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1678, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* AM_SPACING_MUL:9:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 10, 9)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_7_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* R_CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1435, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* R_FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1439, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* R_HG2_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_8_GEN2r_fields[] =
{
    /* CORRUPT_2ND_GROUP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0),
    /* CORRUPT_6TH_GROUP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1),
    /* CL74_SHCORRUPT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 2, 2),
    /* BER_COUNT_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 3, 3),
    /* BER_WINDOW_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 4, 4),
    /* USE_100G_AM0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 5, 5),
    /* USE_100G_AM123:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPD_GEN2r_fields[] =
{
    /* NUM_LANES:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 0),
    /* T_PMA_40B_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 3, 3),
    /* CL36TX_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 4, 4),
    /* CL36RX_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 5, 5),
    /* SPEED:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1492, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0_GEN2r_fields[] =
{
    /* SCR_MODE:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1453, 3, 1),
    /* T_PMA_BTMX_MODE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 5, 4),
    /* T_HG2_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1680, 6, 6),
    /* T_ENC_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 8, 7),
    /* T_FIFO_MODE:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 10, 9),
    /* OS_MODE:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 14, 11),
    /* CL72_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_6_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1670, 0, 0),
    /* T_FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1678, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* AM_SPACING_MUL:9:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 10, 9)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_7_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* R_CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1435, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* R_FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1439, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* R_HG2_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_8_GEN2r_fields[] =
{
    /* CORRUPT_2ND_GROUP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0),
    /* CORRUPT_6TH_GROUP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1),
    /* CL74_SHCORRUPT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 2, 2),
    /* BER_COUNT_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 3, 3),
    /* BER_WINDOW_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 4, 4),
    /* USE_100G_AM0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 5, 5),
    /* USE_100G_AM123:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPD_GEN2r_fields[] =
{
    /* NUM_LANES:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 0),
    /* T_PMA_40B_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 3, 3),
    /* CL36TX_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 4, 4),
    /* CL36RX_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 5, 5),
    /* SPEED:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1492, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0_GEN2r_fields[] =
{
    /* SCR_MODE:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1453, 3, 1),
    /* T_PMA_BTMX_MODE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 5, 4),
    /* T_HG2_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1680, 6, 6),
    /* T_ENC_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 8, 7),
    /* T_FIFO_MODE:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 10, 9),
    /* OS_MODE:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 14, 11),
    /* CL72_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_6_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1670, 0, 0),
    /* T_FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1678, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* AM_SPACING_MUL:9:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 10, 9)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_7_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* R_CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1435, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* R_FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1439, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* R_HG2_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_8_GEN2r_fields[] =
{
    /* CORRUPT_2ND_GROUP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0),
    /* CORRUPT_6TH_GROUP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1),
    /* CL74_SHCORRUPT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 2, 2),
    /* BER_COUNT_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 3, 3),
    /* BER_WINDOW_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 4, 4),
    /* USE_100G_AM0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 5, 5),
    /* USE_100G_AM123:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPD_GEN2r_fields[] =
{
    /* NUM_LANES:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 0),
    /* T_PMA_40B_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 3, 3),
    /* CL36TX_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 4, 4),
    /* CL36RX_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 5, 5),
    /* SPEED:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1492, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0_GEN2r_fields[] =
{
    /* SCR_MODE:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1453, 3, 1),
    /* T_PMA_BTMX_MODE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 5, 4),
    /* T_HG2_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1680, 6, 6),
    /* T_ENC_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 8, 7),
    /* T_FIFO_MODE:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 10, 9),
    /* OS_MODE:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 14, 11),
    /* CL72_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_6_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1670, 0, 0),
    /* T_FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1678, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* AM_SPACING_MUL:9:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 10, 9)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_7_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* R_CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1435, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* R_FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1439, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* R_HG2_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_8_GEN2r_fields[] =
{
    /* CORRUPT_2ND_GROUP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0),
    /* CORRUPT_6TH_GROUP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1),
    /* CL74_SHCORRUPT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 2, 2),
    /* BER_COUNT_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 3, 3),
    /* BER_WINDOW_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 4, 4),
    /* USE_100G_AM0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 5, 5),
    /* USE_100G_AM123:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPD_GEN2r_fields[] =
{
    /* NUM_LANES:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 0),
    /* T_PMA_40B_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 3, 3),
    /* CL36TX_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 4, 4),
    /* CL36RX_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 5, 5),
    /* SPEED:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1492, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_STS_GEN2r_fields[] =
{
    /* RESOLVED_PORT_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1234, 2, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X1_TX_RST_CNT_GEN2r_fields[] =
{
    /* TX_RESET_COUNT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1664, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_BYPASS_GEN2r_fields[] =
{
    /* SC_BYPASS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1455, 0, 0),
    /* SC_IGNORE_TX_DATA_VLD:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1457, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_CTL_GEN2r_fields[] =
{
    /* SPEED:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1492, 7, 0),
    /* SW_SPEED_CHANGE:8:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1501, 8, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_DBG_GEN2r_fields[] =
{
    /* SC_FSM_STATUS:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1456, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_ERR_GEN2r_fields[] =
{
    /* PLL_LOCK_TIMED_OUT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1152, 0, 0),
    /* PMD_LOCK_TIMED_OUT:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1169, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_FEC_STS_GEN2r_fields[] =
{
    /* R_FEC_ENABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1438, 0, 0),
    /* T_FEC_ENABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1675, 1, 1),
    /* R_CL91_FEC_MODE:2:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1437, 4, 2),
    /* T_CL91_FEC_MODE:5:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1672, 7, 5)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPE_GEN2r_fields[] =
{
    /* CL36RX_EN_OEN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(421, 0, 0),
    /* CL36TX_EN_OEN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(428, 1, 1),
    /* T_PMA_40B_MODE_OEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1683, 2, 2),
    /* DEC_FSM_MODE_OEN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(683, 3, 3),
    /* DESKEW_MODE_OEN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(705, 4, 4),
    /* DEC_TL_MODE_OEN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(688, 5, 5),
    /* DESCR_MODE_OEN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(690, 6, 6),
    /* CL72_EN_OEN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(449, 7, 7),
    /* SCR_MODE_OEN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1454, 8, 8),
    /* T_PMA_BTMX_MODE_OEN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1687, 9, 9),
    /* T_HG2_ENABLE_OEN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1681, 10, 10),
    /* T_ENC_MODE_OEN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1674, 11, 11),
    /* T_FIFO_MODE_OEN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1677, 12, 12),
    /* OS_MODE_OEN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1100, 13, 13),
    /* NUM_LANES_OEN:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1077, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPE_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE_OEN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1671, 0, 0),
    /* T_FIVE_BIT_XOR_EN_OEN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1679, 1, 1),
    /* T_PMA_CL91_MUX_SEL_OEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1689, 2, 2),
    /* T_PMA_WATERMARK_OEN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1691, 3, 3),
    /* T_PMA_BITMUX_DELAY_OEN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1685, 4, 4),
    /* MAC_CREDITGENCNT_OEN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(974, 5, 5),
    /* LOOPCNT1_OEN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(950, 6, 6),
    /* LOOPCNT0_OEN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(948, 7, 7),
    /* CLOCKCNT1_OEN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(603, 8, 8),
    /* CLOCKCNT0_OEN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(601, 9, 9),
    /* CREDITENABLE_OEN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(646, 10, 10),
    /* BS_BTMX_MODE_OEN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(353, 11, 11),
    /* BS_DIST_MODE_OEN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(355, 12, 12),
    /* BS_SYNC_EN_OEN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(361, 13, 13),
    /* BS_SM_SYNC_MODE_OEN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(358, 14, 14),
    /* R_HG2_ENABLE_OEN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1442, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN2_TYPE_GEN2r_fields[] =
{
    /* AM_SPACING_MUL_OEN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(220, 0, 0),
    /* CL91_BLKSYNC_MODE_OEN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(499, 1, 1),
    /* R_MERGE_MODE_OEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1444, 2, 2),
    /* R_CL91_CW_SCRAMBLE_OEN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1436, 3, 3),
    /* R_TC_IN_MODE_OEN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1446, 4, 4),
    /* R_TC_MODE_OEN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1448, 5, 5),
    /* R_FIVE_BIT_XOR_EN_OEN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1440, 6, 6),
    /* R_TC_OUT_MODE_OEN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1450, 7, 7),
    /* CORRUPT_2ND_GROUP:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 8, 8),
    /* CORRUPT_6TH_GROUP:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 9, 9),
    /* CL74_SHCORRUPT:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 10, 10),
    /* BER_COUNT_SEL:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 11, 11),
    /* BER_WINDOW_SEL:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 12, 12),
    /* USE_100G_AM0:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 13, 13),
    /* USE_100G_AM123:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_IEEE_25G_CTL_GEN2r_fields[] =
{
    /* CL74_SHCORRUPT_25IEEE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(471, 0, 0),
    /* IEEE_COUNT_SEL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(867, 1, 1),
    /* IEEE_WINDOW_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(869, 2, 2),
    /* IEEE_25G_AM123_FORMAT:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(864, 3, 3),
    /* IEEE_25G_AM0_FORMAT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(863, 4, 4),
    /* IEEE_25G_AM_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(865, 5, 5),
    /* IEEE_25G_5BIT_XOR:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(862, 6, 6),
    /* IEEE_25G_CWSCR_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(866, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_MSA_25G_50G_CTL_GEN2r_fields[] =
{
    /* CL74_SHCORRUPT_25GMSA:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(470, 0, 0),
    /* CL74_SHCORRUPT_50GMSA:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(472, 1, 1),
    /* MSA_COUNT_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1066, 2, 2),
    /* MSA_WINDOW_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1070, 3, 3),
    /* MSA_25G_AM123_FORMAT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1061, 4, 4),
    /* MSA_25G_AM0_FORMAT:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1060, 5, 5),
    /* MSA_50G_AM123_FORMAT:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1065, 6, 6),
    /* MSA_50G_AM0_FORMAT:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1064, 7, 7),
    /* MSA_25G_AM_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1062, 8, 8),
    /* MSA_25G_5BIT_XOR:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1059, 9, 9),
    /* MSA_25G_CWSCR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1063, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_0_GEN2r_fields[] =
{
    /* SCR_MODE:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1453, 3, 1),
    /* T_PMA_BTMX_MODE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 5, 4),
    /* T_HG2_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1680, 6, 6),
    /* T_ENC_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 8, 7),
    /* T_FIFO_MODE:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 10, 9),
    /* OS_MODE:11:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 14, 11),
    /* CL72_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(448, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_1_GEN2r_fields[] =
{
    /* BS_BTMX_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 1, 0),
    /* BS_DIST_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(354, 3, 2),
    /* BS_SYNC_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(360, 4, 4),
    /* BS_SM_SYNC_MODE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(357, 5, 5),
    /* DEC_FSM_MODE:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 7, 6),
    /* DESKEW_MODE:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 11, 8),
    /* DEC_TL_MODE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 13, 12),
    /* DESCR_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 15, 14)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_2_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_3_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_4_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_5_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_6_GEN2r_fields[] =
{
    /* T_CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1670, 0, 0),
    /* T_FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1678, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* AM_SPACING_MUL:9:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 10, 9)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_7_GEN2r_fields[] =
{
    /* CL91_BLKSYNC_MODE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 2, 0),
    /* R_MERGE_MODE:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1443, 5, 3),
    /* R_CL91_CW_SCRAMBLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1435, 6, 6),
    /* R_TC_IN_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1445, 7, 7),
    /* R_TC_MODE:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1447, 9, 8),
    /* R_FIVE_BIT_XOR_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1439, 10, 10),
    /* R_TC_OUT_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1449, 12, 11),
    /* R_HG2_ENABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1441, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_8_GEN2r_fields[] =
{
    /* CORRUPT_2ND_GROUP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 0, 0),
    /* CORRUPT_6TH_GROUP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 1, 1),
    /* CL74_SHCORRUPT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 2, 2),
    /* BER_COUNT_SEL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 3, 3),
    /* BER_WINDOW_SEL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 4, 4),
    /* USE_100G_AM0:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 5, 5),
    /* USE_100G_AM123:6:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 6, 6)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_RSLVD_SPD_GEN2r_fields[] =
{
    /* NUM_LANES:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1076, 2, 0),
    /* T_PMA_40B_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 3, 3),
    /* CL36TX_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 4, 4),
    /* CL36RX_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(420, 5, 5),
    /* SPEED:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1492, 15, 8)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_SC_X4_OVRR_GEN2r_fields[] =
{
    /* NUM_LANES_OVERRIDE_VALUE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1078, 2, 0),
    /* AN_FEC_SEL_OVERRIDE:3:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(231, 4, 3),
    /* CORRUPT_2ND_GROUP:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 5, 5),
    /* CORRUPT_6TH_GROUP:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 6, 6),
    /* CL74_SHCORRUPT:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 7, 7),
    /* BER_COUNT_SEL:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 8, 8),
    /* BER_WINDOW_SEL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 9, 9),
    /* USE_100G_AM0:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1720, 10, 10),
    /* USE_100G_AM123:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1721, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_SPARE0_GEN2r_fields[] =
{
    /* SPARE0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1490, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_SPARE1_GEN2r_fields[] =
{
    /* SPARE1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1491, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_SC_X4_STS_GEN2r_fields[] =
{
    /* SW_SPEED_CHANGE_DONE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1502, 0, 0),
    /* SW_SPEED_CONFIG_VLD:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1503, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL_0_GEN2r_fields[] =
{
    /* SIGNAL_DETECT_FILTER_COUNT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1475, 4, 0),
    /* LOS_FILTER_COUNT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(952, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL_1_GEN2r_fields[] =
{
    /* AFE_SIGNAL_DETECT_DIS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(12, 0, 0),
    /* EXT_LOS_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(793, 1, 1),
    /* EXT_LOS_INV:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(794, 2, 2),
    /* IGNORE_LP_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(871, 3, 3),
    /* SIGNAL_DETECT_FILTER_1US:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1474, 4, 4),
    /* ENERGY_DETECT_FRC:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(762, 5, 5),
    /* ENERGY_DETECT_FRC_VAL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(763, 6, 6),
    /* SIGNAL_DETECT_FRC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1476, 7, 7),
    /* SIGNAL_DETECT_FRC_VAL:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1477, 8, 8),
    /* ENERGY_DETECT_MASK_COUNT:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(764, 15, 11)
};
static uint32_t BCMI_TSCF_XGXS_SIGDET_CTL_2_GEN2r_fields[] =
{
    /* LOS_THRESH:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(953, 2, 0),
    /* SIGNAL_DETECT_THRESH:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1485, 6, 4),
    /* HOLD_LOS_COUNT:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(857, 10, 8),
    /* HOLD_SD_COUNT:11:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(858, 13, 11)
};
static uint32_t BCMI_TSCF_XGXS_SIGDET_STS_0_GEN2r_fields[] =
{
    /* SIGNAL_DETECT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1472, 0, 0),
    /* SIGNAL_DETECT_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1473, 1, 1),
    /* ENERGY_DETECT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(760, 2, 2),
    /* ENERGY_DETECT_CHANGE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(761, 3, 3),
    /* SIGNAL_DETECT_RAW:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1482, 4, 4),
    /* SIGNAL_DETECT_RAW_CHANGE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1483, 5, 5),
    /* AFE_SIGDET_THRESH:8:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(11, 10, 8)
};
static uint32_t BCMI_TSCF_XGXS_TEST1_RXPKTCNT_L_GEN2r_fields[] =
{
    /* RXPKTCNT_L:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1378, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TEST1_RXPKTCNT_U_GEN2r_fields[] =
{
    /* RXPKTCNT_U:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1379, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TEST1_TXPKTCNT_L_GEN2r_fields[] =
{
    /* TXPKTCNT_L:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1608, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TEST1_TXPKTCNT_U_GEN2r_fields[] =
{
    /* TXPKTCNT_U:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1609, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFG_GEN2r_fields[] =
{
    /* DIG_LPBK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(710, 0, 0),
    /* DIG_LPBK_PD_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(714, 1, 1),
    /* DIG_LPBK_PD_BIAS_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(711, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STS_GEN2r_fields[] =
{
    /* DIG_LPBK_PD_LATE_IND:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(713, 0, 0),
    /* DIG_LPBK_PD_EARLY_IND:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(712, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STS_GEN2r_fields[] =
{
    /* MAX_PRBS_BURST_ERR_LENGTH_STATUS:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(976, 5, 0)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_MISC_CFG_GEN2r_fields[] =
{
    /* RX_PMD_DP_INVERT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1425, 0, 0),
    /* DBG_MASK_DIG_LPBK_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(665, 2, 2),
    /* TLB_RX_DIFF_DEC_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1535, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STS_GEN2r_fields[] =
{
    /* PMD_RX_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1174, 0, 0),
    /* PMD_RX_LOCK_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1175, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STS_GEN2r_fields[] =
{
    /* PRBS_BURST_ERR_LENGTH_STATUS:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1181, 5, 0)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFG_GEN2r_fields[] =
{
    /* PRBS_CHK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1184, 0, 0),
    /* PRBS_CHK_MODE_SEL:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1196, 3, 1),
    /* PRBS_CHK_INV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1191, 4, 4),
    /* PRBS_CHK_MODE:5:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1195, 6, 5),
    /* PRBS_CHK_EN_AUTO_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1185, 7, 7),
    /* PRBS_BURST_LEN_CHK_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1182, 8, 8),
    /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1188, 9, 9),
    /* TRNSUM_ERROR_COUNT_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1552, 10, 10),
    /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1183, 11, 11)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFG_GEN2r_fields[] =
{
    /* PRBS_CHK_LOCK_CNT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1193, 4, 0),
    /* PRBS_CHK_OOL_CNT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1197, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTL_GEN2r_fields[] =
{
    /* PRBS_CHK_EN_TIMER_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1187, 1, 0),
    /* PRBS_CHK_EN_TIMEOUT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1186, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STS_GEN2r_fields[] =
{
    /* PRBS_CHK_ERR_CNT_LSB:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1189, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STS_GEN2r_fields[] =
{
    /* PRBS_CHK_ERR_CNT_MSB:0:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1190, 14, 0),
    /* PRBS_CHK_LOCK_LOST_LH:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1194, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STS_GEN2r_fields[] =
{
    /* PRBS_CHK_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1192, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_TLB_TX_MISC_CFG_GEN2r_fields[] =
{
    /* TX_PMD_DP_INVERT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1661, 0, 0),
    /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1630, 1, 1),
    /* TX_MUX_SEL_ORDER:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1628, 2, 2),
    /* TLB_TX_DIFF_ENC_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1536, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFG_GEN2r_fields[] =
{
    /* PATT_GEN_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1106, 0, 0),
    /* PATT_GEN_STOP_POS:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1123, 11, 8),
    /* PATT_GEN_START_POS:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1122, 15, 12)
};
static uint32_t BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFG_GEN2r_fields[] =
{
    /* PRBS_GEN_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1198, 0, 0),
    /* PRBS_GEN_MODE_SEL:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1201, 3, 1),
    /* PRBS_GEN_INV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1200, 4, 4),
    /* PRBS_GEN_ERR_INS:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1199, 5, 5)
};
static uint32_t BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFG_GEN2r_fields[] =
{
    /* RMT_LPBK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1259, 0, 0),
    /* RMT_LPBK_PD_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1263, 1, 1),
    /* RMT_LPBK_PD_FRC_ON:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1261, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STS_GEN2r_fields[] =
{
    /* RMT_LPBK_PD_LATE_IND:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1262, 0, 0),
    /* RMT_LPBK_PD_EARLY_IND:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1260, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL0_GEN2r_fields[] =
{
    /* TXFIR_PRE_OFFSET:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1607, 3, 0),
    /* TXFIR_MAIN_OFFSET:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1595, 7, 4),
    /* TXFIR_POST_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1604, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL1_GEN2r_fields[] =
{
    /* TXFIR_POST2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1596, 4, 0),
    /* TXFIR_POST2_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1598, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_CTL2_GEN2r_fields[] =
{
    /* TXFIR_POST3:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1599, 3, 0),
    /* TXFIR_POST3_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1601, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_MISC_CTL1_GEN2r_fields[] =
{
    /* SDK_TX_DISABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1458, 0, 0),
    /* PMD_TX_DISABLE_PKILL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1178, 1, 1),
    /* TX_DISABLE_TIMER_CTRL:2:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1616, 7, 2),
    /* TX_EEE_QUIET_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1618, 8, 8),
    /* TX_EEE_ALERT_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1617, 9, 9),
    /* TX_DISABLE_OUTPUT_SEL:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1615, 11, 10),
    /* DP_RESET_TX_DISABLE_DIS:12:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(737, 12, 12)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_STS0_GEN2r_fields[] =
{
    /* TXFIR_PRE_AFTER_OVR:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1606, 4, 0),
    /* TXFIR_POST_AFTER_OVR:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1603, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_STS1_GEN2r_fields[] =
{
    /* TXFIR_MAIN_AFTER_OVR:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1594, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_STS2_GEN2r_fields[] =
{
    /* TXFIR_PRE_ADJUSTED:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1605, 4, 0),
    /* TXFIR_POST_ADJUSTED:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1602, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_STS3_GEN2r_fields[] =
{
    /* TXFIR_MAIN_ADJUSTED:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1593, 6, 0),
    /* TXFIR_POST2_ADJUSTED:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1597, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_STS4_GEN2r_fields[] =
{
    /* TXFIR_POST3_ADJUSTED:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1600, 3, 0)
};
static uint32_t BCMI_TSCF_XGXS_TXFIR_UC_CTL0_GEN2r_fields[] =
{
    /* MICRO_TX_DISABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1057, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_CTL0_GEN2r_fields[] =
{
    /* TXCOM_POST_TAP_ALERT_VAL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1587, 5, 0),
    /* TXCOM_PRE_TAP_ALERT_VAL:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1588, 12, 8)
};
static uint32_t BCMI_TSCF_XGXS_TX_CTL1_GEN2r_fields[] =
{
    /* TXCOM_MAIN_TAP_ALERT_VAL:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1586, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_CTL2_GEN2r_fields[] =
{
    /* TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1584, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_CTL3_GEN2r_fields[] =
{
    /* TXCOM_CL93N72_WAIT_CNTR_LIMIT:0:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1585, 8, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL_0_GEN2r_fields[] =
{
    /* TX_PI_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1631, 0, 0),
    /* TX_PI_JITTER_FILTER_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1642, 1, 1),
    /* TX_PI_EXT_CTRL_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1632, 2, 2),
    /* TX_PI_FREQ_OVERRIDE_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1635, 3, 3),
    /* TX_PI_SJ_GEN_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1659, 4, 4),
    /* TX_PI_SSC_GEN_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1660, 5, 5),
    /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1645, 6, 6),
    /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1658, 7, 7),
    /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1634, 9, 8),
    /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1657, 11, 10),
    /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1633, 14, 12)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL_1_GEN2r_fields[] =
{
    /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1636, 14, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL_2_GEN2r_fields[] =
{
    /* TX_PI_JIT_FREQ_IDX:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1644, 5, 0),
    /* TX_PI_JIT_AMP:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1643, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL_3_GEN2r_fields[] =
{
    /* TX_PI_PHASE_OVERRIDE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1651, 0, 0),
    /* TX_PI_PHASE_STROBE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1654, 1, 1),
    /* TX_PI_PHASE_STEP_DIR:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1652, 2, 2),
    /* TX_PI_PHASE_INVERT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1650, 4, 4),
    /* TX_PI_PHASE_STEP_NUM:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1653, 11, 8)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_CTL_4_GEN2r_fields[] =
{
    /* TX_PI_FRZ_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1637, 0, 0),
    /* TX_PI_FRZ_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1638, 1, 1),
    /* TX_PI_FRZ_MODE:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1639, 2, 2),
    /* TX_PI_RESET_CODE_DBG:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1655, 3, 3),
    /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1656, 4, 4)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS_0_GEN2r_fields[] =
{
    /* TX_PI_PHASE_CNTR:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1648, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS_1_GEN2r_fields[] =
{
    /* TX_PI_INTEG1_REG:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1640, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS_2_GEN2r_fields[] =
{
    /* TX_PI_INTEG2_REG:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1641, 14, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_PI_PMD_STS_3_GEN2r_fields[] =
{
    /* TX_PI_PHASE_ERR:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1649, 5, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_X1_TX_LN_SWP_GEN2r_fields[] =
{
    /* LOGICAL0_TO_PHY_SEL:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(943, 1, 0),
    /* LOGICAL1_TO_PHY_SEL:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(944, 3, 2),
    /* LOGICAL2_TO_PHY_SEL:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(945, 5, 4),
    /* LOGICAL3_TO_PHY_SEL:6:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(946, 7, 6)
};
static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_0_GEN2r_fields[] =
{
    /* CL82_TX_RF_ENABLE:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(485, 4, 4),
    /* CL82_TX_LF_ENABLE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(483, 5, 5),
    /* CL82_TX_LI_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(484, 6, 6),
    /* CL82_BYPASS_TXSM:10:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(474, 10, 10)
};
static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_0_GEN2r_fields[] =
{
    /* TXSM_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1610, 2, 0),
    /* T_TYPE_CODED:3:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1694, 5, 3)
};
static uint32_t BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_1_GEN2r_fields[] =
{
    /* LTXSM_STATE:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(972, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_CL36_CTL_GEN2r_fields[] =
{
    /* CL36TX_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 0, 0),
    /* CL36TX_LPI_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(429, 1, 1),
    /* CL36TX_CATCH_ALL_8B10B_DIS:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(426, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_CRED0_GEN2r_fields[] =
{
    /* CLOCKCNT0:0:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(600, 13, 0),
    /* CREDITENABLE:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(645, 14, 14)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_CRED1_GEN2r_fields[] =
{
    /* CLOCKCNT1:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(602, 7, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC_0_GEN2r_fields[] =
{
    /* T_ENC_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1673, 1, 0),
    /* T_FIFO_MODE:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1676, 3, 2),
    /* AM_SPACING_MUL:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(219, 5, 4),
    /* CL49_TX_TL_MODE:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(446, 8, 7),
    /* CL49_BYPASS_TXSM:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(432, 9, 9),
    /* HG2_ENABLE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(848, 10, 10),
    /* HG2_MESSAGE_INVALID_CODE_ENABLE:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(849, 11, 11),
    /* HG2_CODEC:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(847, 12, 12),
    /* BLOCK_NON_FC_BLK_TYPES:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(349, 13, 13),
    /* DIS_SCRAMBLER:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(732, 14, 14),
    /* TX_TEST_MODE_CFG:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1668, 15, 15)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC_STS_0_GEN2r_fields[] =
{
    /* CL49_TXSM_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(441, 2, 0),
    /* CL49_T_TYPE_CODED:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(447, 6, 3),
    /* CL82_IDLE_DELETION_UNDERFLOW:7:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(478, 7, 7)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_ENC_STS_1_GEN2r_fields[] =
{
    /* CL49_LTXSM_STATE:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(433, 7, 0),
    /* CL49_TX_FAULT_DET:8:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(442, 8, 8)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_LOOPCNT_GEN2r_fields[] =
{
    /* LOOPCNT1:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(949, 5, 0),
    /* LOOPCNT0:6:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(947, 13, 6)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNT_GEN2r_fields[] =
{
    /* MAC_CREDITGENCNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(973, 12, 0)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_MISC_GEN2r_fields[] =
{
    /* ENABLE_TX_LANE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(759, 0, 0),
    /* RSTB_TX_LANE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1265, 1, 1),
    /* OS_MODE:2:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1099, 5, 2),
    /* CL49_TX_RF_ENABLE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(445, 6, 6),
    /* CL49_TX_LF_ENABLE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(443, 7, 7),
    /* CL49_TX_LI_ENABLE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(444, 8, 8),
    /* T_PMA_40B_MODE:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1682, 9, 9),
    /* FEC_ENABLE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(804, 10, 10),
    /* T_PMA_BTMX_MODE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1686, 12, 11),
    /* SCR_MODE:13:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1453, 15, 13)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCH_GEN2r_fields[] =
{
    /* LPI_RECEIVED_LH:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(957, 0, 0),
    /* REMOTE_FAULT_LH:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1226, 1, 1),
    /* LOCAL_FAULT_LH:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(941, 2, 2),
    /* LINK_INTERRUPT_LH:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(920, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVE_GEN2r_fields[] =
{
    /* TX_LPI_RECEIVED:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1625, 0, 0),
    /* TX_LINK_INTERRUPT:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1623, 1, 1),
    /* TX_REMOTE_FAULT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1663, 2, 2),
    /* TX_LOCAL_FAULT:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1624, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_PMA_STS_GEN2r_fields[] =
{
    /* T_TC_OUT_OVERFLOW:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1692, 2, 2),
    /* T_TC_OUT_UNDERFLOW:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1693, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_TX_X4_TX_CTL0_GEN2r_fields[] =
{
    /* CL91_CW_SCRAMBLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(512, 0, 0),
    /* FIVE_BIT_XOR_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(832, 1, 1),
    /* T_PMA_CL91_MUX_SEL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1688, 2, 2),
    /* T_PMA_WATERMARK:3:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1690, 6, 3),
    /* T_PMA_BITMUX_DELAY:7:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1684, 8, 7),
    /* CL91_FEC_MODE:9:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(530, 11, 9)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_CTL0_GEN2r_fields[] =
{
    /* MICRO_RA_WRDATASIZE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1034, 1, 0),
    /* MICRO_RA_RDDATASIZE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1029, 5, 4),
    /* MICRO_RA_INIT:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1025, 9, 8),
    /* MICRO_AUTOINC_WRADDR_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(996, 12, 12),
    /* MICRO_AUTOINC_RDADDR_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(995, 13, 13)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_RDADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1027, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSW_GEN2r_fields[] =
{
    /* MICRO_RA_RDADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1028, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_RDDATA_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1030, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSW_GEN2r_fields[] =
{
    /* MICRO_RA_RDDATA_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1031, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_STS0_GEN2r_fields[] =
{
    /* MICRO_RA_INITDONE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1026, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1032, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSW_GEN2r_fields[] =
{
    /* MICRO_RA_WRADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1033, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_WRDATA_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1035, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSW_GEN2r_fields[] =
{
    /* MICRO_RA_WRDATA_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1036, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_CLK_CTL0_GEN2r_fields[] =
{
    /* MICRO_MASTER_CLK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1010, 0, 0),
    /* MICRO_CORE_CLK_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(999, 1, 1)
};
static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1_GEN2r_fields[] =
{
    /* MICRO_RA_ECC_WRDATA:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1024, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0_GEN2r_fields[] =
{
    /* MICRO_ECCG_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1003, 0, 0),
    /* MICRO_ECC_FRC_DISABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1005, 1, 1),
    /* MICRO_ECC_CORRUPT:4:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1004, 5, 4)
};
static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0_GEN2r_fields[] =
{
    /* MICRO_CODE_RAM_ECC_ADDRESS:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(997, 14, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1_GEN2r_fields[] =
{
    /* MICRO_RA_ECC_RDDATA:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1023, 6, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0_GEN2r_fields[] =
{
    /* MICRO_CODE_RAM_TM:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(998, 13, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_PRAMIF_AHB_WRADDR_LSW:2:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1012, 15, 2)
};
static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSW_GEN2r_fields[] =
{
    /* MICRO_PRAMIF_AHB_WRADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1013, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_PRAMIF_CTL0_GEN2r_fields[] =
{
    /* MICRO_PRAMIF_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1014, 0, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_PVT_STS0_GEN2r_fields[] =
{
    /* MICRO_PVT_TEMPDATA_RMI:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1020, 9, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RAM_CTL0_GEN2r_fields[] =
{
    /* MICRO_DR_LOOKTAB_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1001, 0, 0),
    /* MICRO_DR_SIZE:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1002, 13, 8)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1_GEN2r_fields[] =
{
    /* MICRO_M0_HRESP_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1009, 0, 0),
    /* MICRO_SW_PMI_HP_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1054, 1, 1),
    /* MICRO_SW_PMI_HP_EXT_RSTB:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1053, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_AHB_STS1_GEN2r_fields[] =
{
    /* MICRO_M0_DEFAULT_SLAVE_ERROR:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1008, 0, 0),
    /* MICRO_RMI_DEFAULT_SLAVE_ERROR:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1037, 1, 1),
    /* MICRO_PR_DEFAULT_SLAVE_ERROR:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1017, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0_GEN2r_fields[] =
{
    /* MICRO_RMI_MBOX_MSGOUT_INTR_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1048, 0, 0),
    /* MICRO_RMI_ECC_CORR_ERR_INTR_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1038, 4, 4),
    /* MICRO_RMI_ECC_UNCORR_ERR_INTR_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1042, 5, 5),
    /* MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1040, 6, 6),
    /* MICRO_RMI_M0_LOCKUP_INTR_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1044, 8, 8),
    /* MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1046, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0_GEN2r_fields[] =
{
    /* MICRO_RMI_MBOX_MSGOUT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1049, 0, 0),
    /* MICRO_RMI_ECC_CORR_ERR_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1039, 4, 4),
    /* MICRO_RMI_ECC_UNCORR_ERR_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1043, 5, 5),
    /* MICRO_RMI_ECC_MULTIROW_ERR_STATUS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1041, 6, 6),
    /* MICRO_RMI_M0_LOCKUP_STATUS:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1045, 8, 8),
    /* MICRO_RMI_M0_SYSTEMRESETREQ_STATUS:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1047, 9, 9)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0_GEN2r_fields[] =
{
    /* MICRO_RMI_MBOX_SEND_MSGIN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1050, 0, 0),
    /* MICRO_GEN_INTR_RMI_MBOX0WR:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1006, 1, 1),
    /* MICRO_GEN_INTR_RMI_MBOX1WR:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1007, 2, 2)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_PR_AUTOINC_NXT_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1016, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0_GEN2r_fields[] =
{
    /* MICRO_PVT_TEMPDATA_FRCVAL:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1019, 9, 0),
    /* MICRO_PVT_TEMPDATA_FRC:12:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1018, 12, 12)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_AUTOINC_NXT_RDADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1021, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSW_GEN2r_fields[] =
{
    /* MICRO_RA_AUTOINC_NXT_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1022, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0_GEN2r_fields[] =
{
    /* MICRO_RMI_TO_MICRO_MBOX0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1051, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1_GEN2r_fields[] =
{
    /* MICRO_RMI_TO_MICRO_MBOX1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1052, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_RST_CTL0_GEN2r_fields[] =
{
    /* MICRO_MASTER_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1011, 0, 0),
    /* MICRO_CORE_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1000, 1, 1),
    /* MICRO_PRAM_IF_RSTB:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1015, 3, 3)
};
static uint32_t BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0_GEN2r_fields[] =
{
    /* MICRO_TO_RMI_MBOX0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1055, 15, 0)
};
static uint32_t BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1_GEN2r_fields[] =
{
    /* MICRO_TO_RMI_MBOX1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(1056, 15, 0)
};



/*******************************************************************************
 *
 * The following is the field name table.
 */
#if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_TSCF_XGXS
const char* bcmi_tscf_xgxs_gen2_fields[] = 
{
    "ABILITY_DETECT",
    "ACK_DETECT",
    "ACQ_CDR_TIMEOUT",
    "AD_TO_CL73_EN",
    "AFE_RX_PWRDN_FRC",
    "AFE_RX_PWRDN_FRC_VAL",
    "AFE_RX_RCLK20_PWRDN_FRC",
    "AFE_RX_RCLK20_PWRDN_FRC_VAL",
    "AFE_RX_RESET_FRC",
    "AFE_RX_RESET_FRC_VAL",
    "AFE_SIGDET_PWRDN",
    "AFE_SIGDET_THRESH",
    "AFE_SIGNAL_DETECT_DIS",
    "AFE_S_PLL_PWRDN",
    "AFE_S_PLL_RESET_FRC",
    "AFE_S_PLL_RESET_FRC_VAL",
    "AFE_TX_PWRDN_FRC",
    "AFE_TX_PWRDN_FRC_VAL",
    "AFE_TX_RESET_FRC",
    "AFE_TX_RESET_FRC_VAL",
    "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_0",
    "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_1",
    "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_2",
    "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_3",
    "AMRKR_SPACING_ERR_LATCH_MUX_PSLL_4",
    "AMS_PLL_BGINT",
    "AMS_PLL_BGIP",
    "AMS_PLL_BGR_CTATADJ",
    "AMS_PLL_BGR_PTATADJ",
    "AMS_PLL_CAL_AUX",
    "AMS_PLL_CAL_OFF",
    "AMS_PLL_COMP_VTH",
    "AMS_PLL_DRV_HV_DISABLE",
    "AMS_PLL_ENABLE_FTUNE",
    "AMS_PLL_EN_HRZ",
    "AMS_PLL_FORCE_KVH_BW",
    "AMS_PLL_FORCE_RESCAL",
    "AMS_PLL_IMAX_IBIAS",
    "AMS_PLL_IMAX_ICK",
    "AMS_PLL_IMAX_ICKGEN",
    "AMS_PLL_IMAX_ICLKIDRV1",
    "AMS_PLL_IMAX_ICLKINT",
    "AMS_PLL_IMAX_ICLKODRV1",
    "AMS_PLL_IMAX_ICMLDIV",
    "AMS_PLL_IMAX_ICOMP",
    "AMS_PLL_IMAX_ICP",
    "AMS_PLL_IMAX_IOP",
    "AMS_PLL_IMAX_IRXCLKBUF",
    "AMS_PLL_IMIN_IBIAS",
    "AMS_PLL_IMIN_ICK",
    "AMS_PLL_IMIN_ICKGEN",
    "AMS_PLL_IMIN_ICLKIDRV1",
    "AMS_PLL_IMIN_ICLKINT",
    "AMS_PLL_IMIN_ICLKODRV1",
    "AMS_PLL_IMIN_ICMLDIV",
    "AMS_PLL_IMIN_ICOMP",
    "AMS_PLL_IMIN_ICP",
    "AMS_PLL_IMIN_IOP",
    "AMS_PLL_IMIN_IRXCLKBUF",
    "AMS_PLL_IMODE_IBIAS",
    "AMS_PLL_IMODE_ICK",
    "AMS_PLL_IMODE_ICKGEN",
    "AMS_PLL_IMODE_ICLKIDRV1",
    "AMS_PLL_IMODE_ICLKINT",
    "AMS_PLL_IMODE_ICLKODRV1",
    "AMS_PLL_IMODE_ICMLDIV",
    "AMS_PLL_IMODE_ICOMP",
    "AMS_PLL_IMODE_ICP",
    "AMS_PLL_IMODE_IOP",
    "AMS_PLL_IMODE_IRXCLKBUF",
    "AMS_PLL_IQP",
    "AMS_PLL_IVCO",
    "AMS_PLL_KVH",
    "AMS_PLL_KVH_FORCE",
    "AMS_PLL_LOW",
    "AMS_PLL_MIX1P2CR_CTATADJ",
    "AMS_PLL_MIX1P2CR_PTATADJ",
    "AMS_PLL_MIX3P1CR_CTATADJ",
    "AMS_PLL_MIX3P1CR_PTATADJ",
    "AMS_PLL_MIX3P1C_CALR_CTATADJ",
    "AMS_PLL_MIX3P1C_CALR_PTATADJ",
    "AMS_PLL_NDIV",
    "AMS_PLL_PLL2RX_CLKBW",
    "AMS_PLL_RANGE",
    "AMS_PLL_REFH_PLL",
    "AMS_PLL_REFL_PLL",
    "AMS_PLL_RESET",
    "AMS_PLL_SET_CLK4TSC",
    "AMS_PLL_SPARE_101_96",
    "AMS_PLL_SPARE_117_112",
    "AMS_PLL_SPARE_23_22",
    "AMS_PLL_TEST_BG_OPAMP_BIAS",
    "AMS_PLL_TEST_PLL",
    "AMS_PLL_TEST_PNP",
    "AMS_PLL_TEST_PORT_MAX_AMPLITUDE",
    "AMS_PLL_TEST_RX",
    "AMS_PLL_TEST_VC",
    "AMS_PLL_TEST_VREF",
    "AMS_PLL_VBYPASS",
    "AMS_PLL_VCOICTRL",
    "AMS_PLL_VCO_INDICATOR",
    "AMS_PLL_VDDR_BGB",
    "AMS_RX_CLK_BW_CTRL",
    "AMS_RX_CM_VOLTAGE_IBIAS",
    "AMS_RX_D2C_CLKBUF_IBIAS",
    "AMS_RX_DAC4CK_DAT",
    "AMS_RX_DAC4CK_LMS",
    "AMS_RX_DAC4CK_PHS",
    "AMS_RX_DC_COUPLE",
    "AMS_RX_DC_OFFSET",
    "AMS_RX_DC_OFFSET_RANGE",
    "AMS_RX_DFE_HGAIN_EN",
    "AMS_RX_DFE_SLICER_CAL_IBIAS",
    "AMS_RX_DFE_SLICER_IBIAS",
    "AMS_RX_DFE_SUM_BUF_IBIAS",
    "AMS_RX_DFE_TAP_WEIGHT_IBIAS",
    "AMS_RX_DLL_IBIAS",
    "AMS_RX_EN_TAP9DELAY",
    "AMS_RX_EQ_LZ_EN",
    "AMS_RX_FORCE_DC_OFFSET",
    "AMS_RX_MASTER_DIODES_IBIAS",
    "AMS_RX_MET_R_IBIAS",
    "AMS_RX_OFFSET_CORRECTION_IBIAS",
    "AMS_RX_OFFSET_CORRECTION_RESCAL_MUX",
    "AMS_RX_PD_CH_P1",
    "AMS_RX_PEAKING_FILTER_IBIAS",
    "AMS_RX_PEAKING_FILTER_RESCAL_MUX",
    "AMS_RX_PF_CTRL_GRAY",
    "AMS_RX_PHASE_INTERPOLATORS_IBIAS",
    "AMS_RX_PWRDN_FTAP",
    "AMS_RX_RX_OFFSET_PD",
    "AMS_RX_SEL_D2CLP",
    "AMS_RX_SEL_TH4DFE",
    "AMS_RX_SEL_UGBW",
    "AMS_RX_SHORT_VGA_OUTPUT",
    "AMS_RX_SIGDET",
    "AMS_RX_SIGDET_BYPASS",
    "AMS_RX_SIGDET_IBIAS",
    "AMS_RX_SIGDET_POWER_SAVE",
    "AMS_RX_SIGDET_PWRDN",
    "AMS_RX_SIGDET_THRESHOLD",
    "AMS_RX_SPARE_111_104",
    "AMS_RX_SPARE_123",
    "AMS_RX_SPARE_135_134",
    "AMS_RX_SPARE_143_142",
    "AMS_RX_SPARE_151_150",
    "AMS_RX_SPARE_159",
    "AMS_RX_SPARE_16",
    "AMS_RX_SPARE_63",
    "AMS_RX_SPARE_94_90",
    "AMS_RX_SPARE_95",
    "AMS_RX_TAP1_DATA_THRESH_SEL_GRAY",
    "AMS_RX_TBD_IBIAS",
    "AMS_RX_TPORT_EN",
    "AMS_RX_VGA0_IBIAS",
    "AMS_RX_VGA0_RESCAL_MUX",
    "AMS_RX_VGA1_IBIAS",
    "AMS_RX_VGA1_RESCAL_MUX",
    "AMS_RX_VGA2_IBIAS",
    "AMS_RX_VGA2_RESCAL_MUX",
    "AMS_RX_VGA3_IBIAS",
    "AMS_RX_VGA3_RESCAL_MUX",
    "AMS_RX_VGA_10G_BW",
    "AMS_RX_VGA_CTRL_GRAY",
    "AMS_RX_VGA_LOW_GAIN",
    "AMS_RX_VGA_STEP_MODE",
    "AMS_TX_AMP_CTL",
    "AMS_TX_ANA_RESCAL",
    "AMS_TX_CAL_AUX",
    "AMS_TX_CAL_OFF",
    "AMS_TX_DCC_DIS",
    "AMS_TX_DCC_SEL",
    "AMS_TX_DRIVERMODE",
    "AMS_TX_DRV_HV_DISABLE",
    "AMS_TX_ELEC_IDLE_AUX",
    "AMS_TX_IBIAS",
    "AMS_TX_ICML",
    "AMS_TX_ILDO",
    "AMS_TX_LANE_ID",
    "AMS_TX_LDO_VREF",
    "AMS_TX_POST2_COEF",
    "AMS_TX_POST3_COEF",
    "AMS_TX_SEL_EMPH_MODE",
    "AMS_TX_SIGN_POST2",
    "AMS_TX_SIGN_POST3",
    "AMS_TX_SPARE_0",
    "AMS_TX_SPARE_21_19",
    "AMS_TX_SPARE_31",
    "AMS_TX_SPARE_3_1",
    "AMS_TX_SPARE_63_48",
    "AMS_TX_TEST_DATA",
    "AMS_TX_TICKSEL",
    "AMS_TX_VDDR_BGB",
    "AMS_TX_VERSION_ID",
    "AM_LOCK_0",
    "AM_LOCK_1",
    "AM_LOCK_2",
    "AM_LOCK_3",
    "AM_LOCK_4",
    "AM_LOCK_HIS_STATE_PSLL_0",
    "AM_LOCK_HIS_STATE_PSLL_1",
    "AM_LOCK_HIS_STATE_PSLL_2",
    "AM_LOCK_HIS_STATE_PSLL_3",
    "AM_LOCK_HIS_STATE_PSLL_4",
    "AM_LOCK_LH_0",
    "AM_LOCK_LH_1",
    "AM_LOCK_LH_2",
    "AM_LOCK_LH_3",
    "AM_LOCK_LH_4",
    "AM_LOCK_LL_0",
    "AM_LOCK_LL_1",
    "AM_LOCK_LL_2",
    "AM_LOCK_LL_3",
    "AM_LOCK_LL_4",
    "AM_LOCK_STATE_PSLL_0",
    "AM_LOCK_STATE_PSLL_1",
    "AM_LOCK_STATE_PSLL_2",
    "AM_LOCK_STATE_PSLL_3",
    "AM_LOCK_STATE_PSLL_4",
    "AM_SPACING_MUL",
    "AM_SPACING_MUL_OEN",
    "AM_TIMER_INIT_VAL",
    "AN",
    "AN_ACTIVE",
    "AN_COMPLETE",
    "AN_COMPLETED",
    "AN_COMPLETED_SW_EN",
    "AN_COMPLETED_SW_INT",
    "AN_ENABLE",
    "AN_FAIL_COUNT",
    "AN_FAIL_COUNT_LIMIT",
    "AN_FEC_SEL_OVERRIDE",
    "AN_GOOD_CHECK",
    "AN_GOOD_CHECK_TRAP",
    "AN_GOOD_CHK_EN",
    "AN_GOOD_CHK_INT",
    "AN_GOOD_TRAP",
    "AN_HCD_CL72",
    "AN_HCD_DUPLEX",
    "AN_HCD_FEC",
    "AN_HCD_PAUSE",
    "AN_HCD_RES_DISABLE",
    "AN_HCD_SPEED",
    "AN_OUI_OVERRIDE_BAM73_ADV",
    "AN_OUI_OVERRIDE_BAM73_DET",
    "AN_OUI_OVERRIDE_HPAM_ADV",
    "AN_OUI_OVERRIDE_HPAM_DET",
    "AN_PRIORITY_100G_CR4",
    "AN_PRIORITY_100G_HG2_CR4",
    "AN_PRIORITY_100G_HG2_KR4",
    "AN_PRIORITY_100G_KR4",
    "AN_PRIORITY_10G_HG2_KR1",
    "AN_PRIORITY_10G_KR1",
    "AN_PRIORITY_1G_KX1",
    "AN_PRIORITY_20G_CR1",
    "AN_PRIORITY_20G_CR2",
    "AN_PRIORITY_20G_HG2_CR1",
    "AN_PRIORITY_20G_HG2_CR2",
    "AN_PRIORITY_20G_HG2_KR1",
    "AN_PRIORITY_20G_HG2_KR2",
    "AN_PRIORITY_20G_KR1",
    "AN_PRIORITY_20G_KR2",
    "AN_PRIORITY_25G_CR1",
    "AN_PRIORITY_25G_CR1_IEEE",
    "AN_PRIORITY_25G_CRS1_IEEE",
    "AN_PRIORITY_25G_HG2_CR1",
    "AN_PRIORITY_25G_HG2_KR1",
    "AN_PRIORITY_25G_KR1",
    "AN_PRIORITY_25G_KR1_IEEE",
    "AN_PRIORITY_25G_KRS1_IEEE",
    "AN_PRIORITY_40G_CR2",
    "AN_PRIORITY_40G_CR4",
    "AN_PRIORITY_40G_HG2_CR2",
    "AN_PRIORITY_40G_HG2_CR4",
    "AN_PRIORITY_40G_HG2_KR2",
    "AN_PRIORITY_40G_HG2_KR4",
    "AN_PRIORITY_40G_KR2",
    "AN_PRIORITY_40G_KR4",
    "AN_PRIORITY_50G_CR2",
    "AN_PRIORITY_50G_CR4",
    "AN_PRIORITY_50G_HG2_CR2",
    "AN_PRIORITY_50G_HG2_CR4",
    "AN_PRIORITY_50G_HG2_KR2",
    "AN_PRIORITY_50G_HG2_KR4",
    "AN_PRIORITY_50G_KR2",
    "AN_PRIORITY_50G_KR4",
    "AN_RETRY_COUNT",
    "AN_TYPE_SW",
    "BAM_20G_CR1",
    "BAM_20G_CR2",
    "BAM_20G_KR1",
    "BAM_20G_KR2",
    "BAM_25G_CR1",
    "BAM_25G_KR1",
    "BAM_40G_CR2",
    "BAM_40G_KR2",
    "BAM_50G_CR2",
    "BAM_50G_CR4",
    "BAM_50G_KR2",
    "BAM_50G_KR4",
    "BAM_HG2",
    "BAM_TO_HPAM_AD_EN",
    "BASE_100G_CR4",
    "BASE_100G_KR4",
    "BASE_10G_KR1",
    "BASE_1G_KX1",
    "BASE_25G_CR1_EN",
    "BASE_25G_CR1_SEL",
    "BASE_25G_CRS1_EN",
    "BASE_25G_CRS1_SEL",
    "BASE_25G_KR1_EN",
    "BASE_25G_KR1_SEL",
    "BASE_25G_KRS1_EN",
    "BASE_25G_KRS1_SEL",
    "BASE_40G_CR4",
    "BASE_40G_KR4",
    "BASE_50G_CR2_EN",
    "BASE_50G_CR2_SEL",
    "BASE_50G_KR2_EN",
    "BASE_50G_KR2_SEL",
    "BASE_R_FEC_REQ_EN",
    "BASE_R_FEC_REQ_SEL",
    "BERMON_CURRENT_STATE",
    "BERMON_HISTORY_STATE",
    "BER_COUNT_SEL",
    "BER_HO",
    "BER_LO",
    "BER_WINDOW_SEL",
    "BIP_ERROR_COUNT_0",
    "BIP_ERROR_COUNT_1",
    "BIP_ERROR_COUNT_2",
    "BIP_ERROR_COUNT_3",
    "BIP_ERROR_COUNT_4",
    "BLK_LOCK_ON_CTRL",
    "BLOCK_LOCK_0",
    "BLOCK_LOCK_1",
    "BLOCK_LOCK_2",
    "BLOCK_LOCK_3",
    "BLOCK_LOCK_4",
    "BLOCK_LOCK_LH_0",
    "BLOCK_LOCK_LH_1",
    "BLOCK_LOCK_LH_2",
    "BLOCK_LOCK_LH_3",
    "BLOCK_LOCK_LH_4",
    "BLOCK_LOCK_LL_0",
    "BLOCK_LOCK_LL_1",
    "BLOCK_LOCK_LL_2",
    "BLOCK_LOCK_LL_3",
    "BLOCK_LOCK_LL_4",
    "BLOCK_NON_FC_BLK_TYPES",
    "BONDING",
    "BR_PD_EN",
    "BS_BTMX_MODE",
    "BS_BTMX_MODE_OEN",
    "BS_DIST_MODE",
    "BS_DIST_MODE_OEN",
    "BS_PMD_LOCK",
    "BS_SM_SYNC_MODE",
    "BS_SM_SYNC_MODE_OEN",
    "BS_STATUS",
    "BS_SYNC_EN",
    "BS_SYNC_EN_OEN",
    "BURST_ERR_STATUSH_STREAM0",
    "BURST_ERR_STATUSH_STREAM1",
    "BURST_ERR_STATUSH_STREAM2",
    "BURST_ERR_STATUSH_STREAM3",
    "BURST_ERR_STATUSH_STREAM4",
    "BURST_ERR_STATUSL_STREAM0",
    "BURST_ERR_STATUSL_STREAM1",
    "BURST_ERR_STATUSL_STREAM2",
    "BURST_ERR_STATUSL_STREAM3",
    "BURST_ERR_STATUSL_STREAM4",
    "BURST_ERR_STATUS_MODE",
    "BYPASS_CL49RXSM",
    "BYPASS_CL82RXSM",
    "BYTE0",
    "BYTE1",
    "CAP_CNT_MASK_EN",
    "CAP_DONE",
    "CAP_DONE_LH_LL",
    "CAP_FORCE_SLOWDOWN",
    "CAP_FORCE_SLOWDOWN_EN",
    "CAP_PASS",
    "CAP_PASS_LH_LL",
    "CAP_RESTART",
    "CAP_RETRY_EN",
    "CAP_SELECT",
    "CAP_SELECT_M",
    "CAP_SELECT_M_EN",
    "CAP_SEQ_CYA",
    "CDR_1G_FORCE_EN",
    "CDR_1G_MANUAL_MODE",
    "CDR_1G_MANUAL_STROBE",
    "CDR_1G_PHASE_POINTER",
    "CDR_1G_SWAP_PZ",
    "CDR_1G_TRNSUM_EN",
    "CDR_BWSEL_INTEG_ACQCDR",
    "CDR_BWSEL_INTEG_EEE_ACQCDR",
    "CDR_BWSEL_INTEG_NORM",
    "CDR_BWSEL_PROP_ACQCDR",
    "CDR_BWSEL_PROP_EEE_ACQCDR",
    "CDR_BWSEL_PROP_NORM",
    "CDR_FREQ_EN",
    "CDR_FREQ_OVERRIDE_EN",
    "CDR_FREQ_OVERRIDE_VAL",
    "CDR_FRZ_FRC",
    "CDR_FRZ_FRC_VAL",
    "CDR_INTEG_REG",
    "CDR_INTEG_REG_CLR",
    "CDR_INTEG_SAT_SEL",
    "CDR_LM_OUTOFLOCK",
    "CDR_LM_THR_SEL",
    "CDR_PHASE_ERROR",
    "CDR_PHASE_ERR_FRZ",
    "CDR_SETTLE_TIMEOUT",
    "CDR_VCO_REG",
    "CDR_ZERO_POLARITY",
    "CL36RX_BER_COUNT_PER_LN",
    "CL36RX_BER_EN",
    "CL36RX_DISABLE_CARRIER_EXTEND",
    "CL36RX_EN",
    "CL36RX_EN_OEN",
    "CL36RX_FORCE_COMMA_ALIGN_ENABLE",
    "CL36RX_LPI_EN",
    "CL36RX_SYNCACQ_HIS_STATE_PER_LN",
    "CL36RX_SYNCACQ_STATE_CODED_PER_LN",
    "CL36TX_CATCH_ALL_8B10B_DIS",
    "CL36TX_EN",
    "CL36TX_EN_OEN",
    "CL36TX_LPI_EN",
    "CL49_BER_COUNT",
    "CL49_BER_LIMIT",
    "CL49_BYPASS_TXSM",
    "CL49_LTXSM_STATE",
    "CL49_RXSM_CURRENT_STATE",
    "CL49_RXSM_HISTORY_STATE",
    "CL49_RX_LF_ENABLE",
    "CL49_RX_LI_ENABLE",
    "CL49_RX_RF_ENABLE",
    "CL49_R_TYPE_CODED",
    "CL49_SCRIDLE_TEST_ERR",
    "CL49_TXSM_STATE",
    "CL49_TX_FAULT_DET",
    "CL49_TX_LF_ENABLE",
    "CL49_TX_LI_ENABLE",
    "CL49_TX_RF_ENABLE",
    "CL49_TX_TL_MODE",
    "CL49_T_TYPE_CODED",
    "CL72_EN",
    "CL72_EN_OEN",
    "CL72_TIMER_EN",
    "CL73_AN_COMPLETE",
    "CL73_AN_RESTART",
    "CL73_BAM_CODE",
    "CL73_BAM_ENABLE",
    "CL73_BASE_SELECTOR",
    "CL73_BREAK_TIMER_PERIOD",
    "CL73_ENABLE",
    "CL73_ERROR_TIMER_PERIOD",
    "CL73_FIFO_FULL",
    "CL73_HPAM_ENABLE",
    "CL73_NONCE_MATCH_OVER",
    "CL73_NONCE_MATCH_VAL",
    "CL73_PAGE_TEST_MAX_TIMER",
    "CL73_PAGE_TEST_MIN_TIMER",
    "CL73_PAUSE",
    "CL73_REMOTE_FAULT",
    "CL73_VCO",
    "CL74_REQ",
    "CL74_SHCORRUPT",
    "CL74_SHCORRUPT_25GMSA",
    "CL74_SHCORRUPT_25IEEE",
    "CL74_SHCORRUPT_50GMSA",
    "CL82_BER_LIMIT",
    "CL82_BYPASS_TXSM",
    "CL82_DSWIN",
    "CL82_DSWIN_100G",
    "CL82_DSWIN_CL91",
    "CL82_IDLE_DELETION_UNDERFLOW",
    "CL82_RX_LF_ENABLE",
    "CL82_RX_LI_ENABLE",
    "CL82_RX_RF_ENABLE",
    "CL82_SCRIDLE_TEST_ERR",
    "CL82_TX_LF_ENABLE",
    "CL82_TX_LI_ENABLE",
    "CL82_TX_RF_ENABLE",
    "CL91_40B_ERRGEN_EN_P0",
    "CL91_40B_ERRGEN_EN_P1",
    "CL91_40B_ERRGEN_EN_P2",
    "CL91_40B_ERRGEN_EN_P3",
    "CL91_80B_ERRGEN_EN_P0",
    "CL91_80B_ERRGEN_EN_P1",
    "CL91_80B_ERRGEN_EN_P2",
    "CL91_80B_ERRGEN_EN_P3",
    "CL91_AMPS_LOCK_LH",
    "CL91_AMPS_LOCK_LIVE",
    "CL91_AMPS_LOCK_LL",
    "CL91_AM_SPACING_1024",
    "CL91_BLKSYNC_MODE",
    "CL91_BLKSYNC_MODE_OEN",
    "CL91_BUFFER_BLK0_1BIT_INT_EN",
    "CL91_BUFFER_BLK0_1BIT_INT_STATUS",
    "CL91_BUFFER_BLK0_2BIT_INT_EN",
    "CL91_BUFFER_BLK0_2BIT_INT_STATUS",
    "CL91_BUFFER_BLK1_1BIT_INT_EN",
    "CL91_BUFFER_BLK1_1BIT_INT_STATUS",
    "CL91_BUFFER_BLK1_2BIT_INT_EN",
    "CL91_BUFFER_BLK1_2BIT_INT_STATUS",
    "CL91_BUFFER_BLK2_1BIT_INT_EN",
    "CL91_BUFFER_BLK2_1BIT_INT_STATUS",
    "CL91_BUFFER_BLK2_2BIT_INT_EN",
    "CL91_BUFFER_BLK2_2BIT_INT_STATUS",
    "CL91_CW_SCRAMBLE",
    "CL91_FC_CW_BAD_CNT",
    "CL91_FC_CW_GOOD_CNT",
    "CL91_FC_CW_SYNC_LH",
    "CL91_FC_CW_SYNC_LIVE",
    "CL91_FC_CW_SYNC_LL",
    "CL91_FC_LOCK_CORR_CW",
    "CL91_FC_SLIP_CNT",
    "CL91_FC_SYNC_LATCHED_STATE",
    "CL91_FC_SYNC_LIVE_STATE",
    "CL91_FEC_ALGN_FSM_LATCHED_STATE",
    "CL91_FEC_ALGN_FSM_LIVE_STATE",
    "CL91_FEC_CORR_BIT_CNTR_LOWER",
    "CL91_FEC_CORR_BIT_CNTR_UPPER",
    "CL91_FEC_CORR_CW_CNTR_LOWER",
    "CL91_FEC_CORR_CW_CNTR_UPPER",
    "CL91_FEC_LANE_MAP",
    "CL91_FEC_LANE_MAP_VALID",
    "CL91_FEC_MODE",
    "CL91_FEC_RAM1_HI_1BIT_INT_EN",
    "CL91_FEC_RAM1_HI_1BIT_INT_STATUS",
    "CL91_FEC_RAM1_HI_2BIT_INT_EN",
    "CL91_FEC_RAM1_HI_2BIT_INT_STATUS",
    "CL91_FEC_RAM1_LO_1BIT_INT_EN",
    "CL91_FEC_RAM1_LO_1BIT_INT_STATUS",
    "CL91_FEC_RAM1_LO_2BIT_INT_EN",
    "CL91_FEC_RAM1_LO_2BIT_INT_STATUS",
    "CL91_FEC_RAM2_HI_1BIT_INT_EN",
    "CL91_FEC_RAM2_HI_1BIT_INT_STATUS",
    "CL91_FEC_RAM2_HI_2BIT_INT_EN",
    "CL91_FEC_RAM2_HI_2BIT_INT_STATUS",
    "CL91_FEC_RAM2_LO_1BIT_INT_EN",
    "CL91_FEC_RAM2_LO_1BIT_INT_STATUS",
    "CL91_FEC_RAM2_LO_2BIT_INT_EN",
    "CL91_FEC_RAM2_LO_2BIT_INT_STATUS",
    "CL91_FEC_SYNC_FSM_LATCHED_STATE",
    "CL91_FEC_SYNC_FSM_LIVE_STATE",
    "CL91_FEC_UNCORR_CW_CNTR_LOWER",
    "CL91_FEC_UNCORR_CW_CNTR_UPPER",
    "CL91_REQ",
    "CL93N72_BAD_MARKER_CNT",
    "CL93N72_BRK_RING_OSC",
    "CL93N72_CL93PRBS_POLY_SEL",
    "CL93N72_CTRL_FRAME_DLY",
    "CL93N72_DIS_MAX_WAIT_TIMER",
    "CL93N72_DME_CELL_BOUNDARY_CHK",
    "CL93N72_FRAME_CONSISTENCY_CHK_EN",
    "CL93N72_FRAME_LOCK",
    "CL93N72_GOOD_MARKER_CNT",
    "CL93N72_IEEE_FRAME_LOCK",
    "CL93N72_IEEE_LD_COEFF_UPDATE",
    "CL93N72_IEEE_LD_STATUS_REPORT",
    "CL93N72_IEEE_LP_COEFF_UPDATE",
    "CL93N72_IEEE_LP_STATUS_REPORT",
    "CL93N72_IEEE_RECEIVER_STATUS",
    "CL93N72_IEEE_RESTART_TRAINING",
    "CL93N72_IEEE_TRAINING_ENABLE",
    "CL93N72_IEEE_TRAINING_FAILURE",
    "CL93N72_IEEE_TRAINING_STATUS",
    "CL93N72_LD_XMT_STATUS_PAGE",
    "CL93N72_LOCAL_RX_READY",
    "CL93N72_MICRO_FRAME_LOCK_INT_EN",
    "CL93N72_MICRO_FRAME_LOCK_LSTATUS",
    "CL93N72_MICRO_STATUS_CHG_INT_EN",
    "CL93N72_MICRO_STATUS_CHG_LSTATUS",
    "CL93N72_MICRO_UPDATE_CHG_INT_EN",
    "CL93N72_MICRO_UPDATE_CHG_LSTATUS",
    "CL93N72_PPM_OFFSET_EN",
    "CL93N72_PRBS_MODE_SEL",
    "CL93N72_PRBS_SEED_SEL",
    "CL93N72_PRBS_SEED_VAL",
    "CL93N72_RX_DP_LN_CLK_EN",
    "CL93N72_RX_SIGNAL_OK",
    "CL93N72_RX_TRAINING_EN",
    "CL93N72_STRICT_DME_CHK",
    "CL93N72_STRICT_MARKER_CHK",
    "CL93N72_SW_FRAME_LOCK",
    "CL93N72_SW_REMOTE_RX_READY",
    "CL93N72_SW_RX_TRAINED",
    "CL93N72_TRAINING_FSM_SIGNAL_DETECT",
    "CL93N72_TR_COARSE_LOCK",
    "CL93N72_TXFIR_MAIN",
    "CL93N72_TXFIR_POST",
    "CL93N72_TXFIR_PRE",
    "CL93N72_TX_DP_LN_CLK_EN",
    "CL93N72_XMT_UPDATE_PAGE",
    "CLAUSE22",
    "CLK_TRANS_MISS",
    "CLOCKCNT0",
    "CLOCKCNT0_OEN",
    "CLOCKCNT1",
    "CLOCKCNT1_OEN",
    "CLR_CRCCNT",
    "CLR_RXCNT",
    "CLR_TXCNT",
    "COMPLETE_ACK",
    "CONSISTENCY_MISMATCH",
    "CORCOUNTH_STREAM0",
    "CORCOUNTH_STREAM1",
    "CORCOUNTH_STREAM2",
    "CORCOUNTH_STREAM3",
    "CORCOUNTH_STREAM4",
    "CORCOUNTL_STREAM0",
    "CORCOUNTL_STREAM1",
    "CORCOUNTL_STREAM2",
    "CORCOUNTL_STREAM3",
    "CORCOUNTL_STREAM4",
    "CORE_DP_H_RSTB",
    "CORE_DP_H_RSTB_OEN",
    "CORE_DP_RESET_STATE",
    "CORE_DP_S_RSTB",
    "CORE_MODE",
    "CORE_MODE_OEN",
    "CORE_MULTICAST_MASK_CONTROL",
    "CORE_REG_RESET_OCCURRED",
    "CORE_S_RSTB",
    "CORRUPT_2ND_GROUP",
    "CORRUPT_6TH_GROUP",
    "CORRUPT_ECC_CL91_BUFFER_BLK0",
    "CORRUPT_ECC_CL91_BUFFER_BLK1",
    "CORRUPT_ECC_CL91_BUFFER_BLK2",
    "CORRUPT_ECC_CL91_FEC_RAM1_HI",
    "CORRUPT_ECC_CL91_FEC_RAM1_LO",
    "CORRUPT_ECC_CL91_FEC_RAM2_HI",
    "CORRUPT_ECC_CL91_FEC_RAM2_LO",
    "CORRUPT_ECC_DESKEW_MEM_0",
    "CORRUPT_ECC_DESKEW_MEM_1",
    "CORRUPT_ECC_DESKEW_MEM_2",
    "CORRUPT_ECC_FEC_MEM_0",
    "CORRUPT_ECC_FEC_MEM_1",
    "CORRUPT_ECC_FEC_MEM_2",
    "CORRUPT_ECC_FEC_MEM_3",
    "CRCERRCNT",
    "CREDITENABLE",
    "CREDITENABLE_OEN",
    "CREDIT_EN",
    "CURRENT_RXSM_STATE",
    "DATA_THRESH_SEL_VAL",
    "DATA_THRESH_WRITE",
    "DBG_CAP_STATE_ONE_HOT",
    "DBG_ENABLE_PER_STREAM",
    "DBG_ERRH_STREAM0",
    "DBG_ERRH_STREAM1",
    "DBG_ERRH_STREAM2",
    "DBG_ERRH_STREAM3",
    "DBG_ERRH_STREAM4",
    "DBG_ERRL_STREAM0",
    "DBG_ERRL_STREAM1",
    "DBG_ERRL_STREAM2",
    "DBG_ERRL_STREAM3",
    "DBG_ERRL_STREAM4",
    "DBG_ERR_MODE",
    "DBG_FDBCK",
    "DBG_MASK_DIG_LPBK_EN",
    "DBG_PLL_STATE_ONE_HOT",
    "DBG_SLOWDN",
    "DBG_SLOWDN_CHANGE",
    "DC_OFFSET_BIN",
    "DC_OFFS_ACC_CLR",
    "DC_OFFS_EN",
    "DC_OFFS_GAIN",
    "DC_OFFS_GRADIENT_INVERT",
    "DC_OFFS_HYS_EN",
    "DC_OFFS_HYS_MAG",
    "DC_OFFS_WRITE_EN",
    "DC_OFFS_WRITE_FRC_EN",
    "DC_OFFS_WRITE_VAL",
    "DEC_17B_BURST_GAP_COUNT",
    "DEC_18B_BURST_GAP_COUNT",
    "DEC_19B_BURST_GAP_COUNT",
    "DEC_FSM_MODE",
    "DEC_FSM_MODE_OEN",
    "DEC_GAP_COUNT_MODE",
    "DEC_MAX_PM",
    "DEC_PM_MODE",
    "DEC_TL_MODE",
    "DEC_TL_MODE_OEN",
    "DESCR_MODE",
    "DESCR_MODE_OEN",
    "DESKEW_HIS_STATE",
    "DESKEW_MEM_0_1BIT_INT_EN",
    "DESKEW_MEM_0_1BIT_INT_STATUS",
    "DESKEW_MEM_0_2BIT_INT_EN",
    "DESKEW_MEM_0_2BIT_INT_STATUS",
    "DESKEW_MEM_1_1BIT_INT_EN",
    "DESKEW_MEM_1_1BIT_INT_STATUS",
    "DESKEW_MEM_1_2BIT_INT_EN",
    "DESKEW_MEM_1_2BIT_INT_STATUS",
    "DESKEW_MEM_2_1BIT_INT_EN",
    "DESKEW_MEM_2_1BIT_INT_STATUS",
    "DESKEW_MEM_2_2BIT_INT_EN",
    "DESKEW_MEM_2_2BIT_INT_STATUS",
    "DESKEW_MODE",
    "DESKEW_MODE_OEN",
    "DESKEW_STATE",
    "DESKEW_STATUS",
    "DESKEW_STATUS_LH",
    "DESKEW_STATUS_LL",
    "DIG_LPBK_EN",
    "DIG_LPBK_PD_BIAS_EN",
    "DIG_LPBK_PD_EARLY_IND",
    "DIG_LPBK_PD_LATE_IND",
    "DIG_LPBK_PD_MODE",
    "DISABLE_CL49_BERMON",
    "DISABLE_ECC_CL91_BUFFER_BLK0",
    "DISABLE_ECC_CL91_BUFFER_BLK1",
    "DISABLE_ECC_CL91_BUFFER_BLK2",
    "DISABLE_ECC_CL91_FEC_RAM1_HI",
    "DISABLE_ECC_CL91_FEC_RAM1_LO",
    "DISABLE_ECC_CL91_FEC_RAM2_HI",
    "DISABLE_ECC_CL91_FEC_RAM2_LO",
    "DISABLE_ECC_DESKEW_MEM_0",
    "DISABLE_ECC_DESKEW_MEM_1",
    "DISABLE_ECC_DESKEW_MEM_2",
    "DISABLE_ECC_FEC_MEM_0",
    "DISABLE_ECC_FEC_MEM_1",
    "DISABLE_ECC_FEC_MEM_2",
    "DISABLE_ECC_FEC_MEM_3",
    "DISABLE_REMOTE_FAULT",
    "DIS_CL82_BERMON",
    "DIS_SCRAMBLER",
    "DME_LOCKED",
    "DME_MV_PAIR",
    "DME_PAGE",
    "DME_STATE",
    "DP_RESET_TX_DISABLE_DIS",
    "DSC_CLR_FRC",
    "DSC_CLR_FRC_VAL",
    "DSC_SM_GP_UC_REQ",
    "DSC_SM_READY_FOR_CMD",
    "DSC_SM_SCRATCH",
    "DSC_STATE",
    "DSC_STATE_EEE_ONE_HOT",
    "DSC_STATE_ONE_HOT",
    "DTE_XS",
    "EEE_ACQ_CDR_TIMEOUT",
    "EEE_ANA_PWR_TIMEOUT",
    "EEE_CDR_SETTLE_TIMEOUT",
    "EEE_HW_TUNE_TIMEOUT",
    "EEE_LFSR_CNT",
    "EEE_MEASURE_CNT",
    "EEE_MEASURE_EN",
    "EEE_MODE_EN",
    "EEE_PHASE_ERR_OFFSET",
    "EEE_PHASE_ERR_OFFSET_EN",
    "EEE_QUIET_FROM_EEE_STATES",
    "EEE_QUIET_RX_AFE_PWRDWN_VAL",
    "ENABLE_TX_LANE",
    "ENERGY_DETECT",
    "ENERGY_DETECT_CHANGE",
    "ENERGY_DETECT_FRC",
    "ENERGY_DETECT_FRC_VAL",
    "ENERGY_DETECT_MASK_COUNT",
    "ERRGEN_EN_PH0",
    "ERRGEN_EN_PH1",
    "ERRGEN_EN_PH2",
    "ERRGEN_EN_PH3",
    "ERRORED_BLOCKS_HO",
    "ERRORED_BLOCKS_HO_PRESENT",
    "ERROR_EN_OVR_PER_STREAM",
    "ERROR_EN_OVR_VAL_PER_STREAM",
    "ERROR_MASK_15_0",
    "ERROR_MASK_31_16",
    "ERROR_MASK_47_32",
    "ERROR_MASK_63_48",
    "ERROR_MASK_65_64",
    "ERROR_STATE",
    "ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_0",
    "ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_1",
    "ERR_EVENT_ADDRESS_CL91_BUFFER_BLK_2",
    "ERR_EVENT_ADDRESS_CL91_FEC_RAM1_HI",
    "ERR_EVENT_ADDRESS_CL91_FEC_RAM1_LO",
    "ERR_EVENT_ADDRESS_CL91_FEC_RAM2_HI",
    "ERR_EVENT_ADDRESS_CL91_FEC_RAM2_LO",
    "ERR_EVENT_ADDRESS_DESKEW_0",
    "ERR_EVENT_ADDRESS_DESKEW_1",
    "ERR_EVENT_ADDRESS_DESKEW_2",
    "ERR_EVENT_ADDRESS_FEC_0",
    "ERR_EVENT_ADDRESS_FEC_1",
    "ERR_EVENT_ADDRESS_FEC_2",
    "ERR_EVENT_ADDRESS_FEC_3",
    "EXT_LOS_EN",
    "EXT_LOS_INV",
    "FAST_SEARCH_MODE",
    "FEC_ALIGN_STATUS_LH",
    "FEC_ALIGN_STATUS_LIVE",
    "FEC_ALIGN_STATUS_LL",
    "FEC_BYP_CORR_ABILITY",
    "FEC_BYP_CORR_EN",
    "FEC_BYP_IND_ABILITY",
    "FEC_BYP_IND_EN",
    "FEC_DBG_BYP_CORR",
    "FEC_ENABLE",
    "FEC_ERROR_CODE_ALL_PER_STREAM",
    "FEC_ERR_ENABLE_PER_STREAM",
    "FEC_MEM_0_1BIT_INT_EN",
    "FEC_MEM_0_1BIT_INT_STATUS",
    "FEC_MEM_0_2BIT_INT_EN",
    "FEC_MEM_0_2BIT_INT_STATUS",
    "FEC_MEM_1_1BIT_INT_EN",
    "FEC_MEM_1_1BIT_INT_STATUS",
    "FEC_MEM_1_2BIT_INT_EN",
    "FEC_MEM_1_2BIT_INT_STATUS",
    "FEC_MEM_2_1BIT_INT_EN",
    "FEC_MEM_2_1BIT_INT_STATUS",
    "FEC_MEM_2_2BIT_INT_EN",
    "FEC_MEM_2_2BIT_INT_STATUS",
    "FEC_MEM_3_1BIT_INT_EN",
    "FEC_MEM_3_1BIT_INT_STATUS",
    "FEC_MEM_3_2BIT_INT_EN",
    "FEC_MEM_3_2BIT_INT_STATUS",
    "FEC_REQ",
    "FEC_SYMBOL_ERROR_COUNTER_LOWER_0",
    "FEC_SYMBOL_ERROR_COUNTER_LOWER_1",
    "FEC_SYMBOL_ERROR_COUNTER_LOWER_2",
    "FEC_SYMBOL_ERROR_COUNTER_LOWER_3",
    "FEC_SYMBOL_ERROR_COUNTER_UPPER_0",
    "FEC_SYMBOL_ERROR_COUNTER_UPPER_1",
    "FEC_SYMBOL_ERROR_COUNTER_UPPER_2",
    "FEC_SYMBOL_ERROR_COUNTER_UPPER_3",
    "FIVE_BIT_XOR_EN",
    "FREQ_DET_RESTART_EN",
    "FREQ_DET_RETRY_EN",
    "FREQ_DONE_SM",
    "FREQ_DONE_SM_LH_LL",
    "FREQ_MONITOR_EN",
    "FREQ_PASS_SM",
    "FREQ_PASS_SM_LH_LL",
    "FREQ_UPD_EN_FRC",
    "FREQ_UPD_EN_FRC_VAL",
    "GOOD_PARITY_CNT",
    "HCD_CL91_EN",
    "HCD_DBG_CL74_BASE_EN",
    "HCD_DBG_CL74_UP_EN",
    "HEARTBEAT_COUNT_1US",
    "HG2_CODEC",
    "HG2_ENABLE",
    "HG2_MESSAGE_INVALID_CODE_ENABLE",
    "HISTORY_RXSM_STATE",
    "HI_BER",
    "HI_BER_LH",
    "HI_BER_LL",
    "HI_SER_LH",
    "HI_SER_LIVE",
    "HI_SER_LL",
    "HOLD_LOS_COUNT",
    "HOLD_SD_COUNT",
    "HP_MODE",
    "HW_TUNE_EN",
    "HW_TUNE_TIMEOUT",
    "IEEE_25G_5BIT_XOR",
    "IEEE_25G_AM0_FORMAT",
    "IEEE_25G_AM123_FORMAT",
    "IEEE_25G_AM_EN",
    "IEEE_25G_CWSCR_EN",
    "IEEE_COUNT_SEL",
    "IEEE_ERRORED_BLOCKS",
    "IEEE_WINDOW_SEL",
    "IGNORE_LINK_TIMER_PERIOD",
    "IGNORE_LP_MODE",
    "IGNORE_RX_MODE",
    "ILKN_SEL",
    "INT_PORT0",
    "INT_PORT0_MASK",
    "INT_PORT1",
    "INT_PORT1_MASK",
    "INT_PORT2",
    "INT_PORT2_MASK",
    "INT_PORT3",
    "INT_PORT3_MASK",
    "INVALID_PARITY_CNT",
    "INV_RX_ORDER",
    "INV_TX_ORDER",
    "IPG_SIZE",
    "LANE0_DEBUG_INFO",
    "LANE1_DEBUG_INFO",
    "LANE2_DEBUG_INFO",
    "LANE3_DEBUG_INFO",
    "LANE4_DEBUG_INFO",
    "LANE_0_AM_1_0",
    "LANE_0_AM_2",
    "LANE_1_AM_1_0",
    "LANE_1_AM_2",
    "LANE_ADDR_0",
    "LANE_ADDR_1",
    "LANE_ADDR_2",
    "LANE_ADDR_3",
    "LANE_DP_RESET_STATE",
    "LANE_MODE",
    "LANE_MODE_OEN",
    "LANE_MULTICAST_MASK_CONTROL",
    "LANE_REG_RESET_OCCURRED",
    "LANE_RESET_RELEASED",
    "LANE_RESET_RELEASED_INDEX",
    "LATCH_LINKDOWN_ENABLE",
    "LD_CONTROL_VALID",
    "LD_PAGE_0",
    "LD_PAGE_1",
    "LD_PAGE_2",
    "LD_PAGE_REQ",
    "LD_PAGE_REQ_EN",
    "LD_PAGE_REQ_INT",
    "LD_SEQ_RESTART",
    "LINKFAILTIMERQUAL_EN",
    "LINKFAILTIMER_DIS",
    "LINK_FAIL_INHIBIT_TIMER_CL72_PERIOD",
    "LINK_FAIL_INHIBIT_TIMER_NCL72_PERIOD",
    "LINK_INTERRUPT",
    "LINK_INTERRUPT_LH",
    "LINK_STATUS",
    "LINK_STATUS_LH",
    "LINK_STATUS_LL",
    "LN_DP_H_RSTB",
    "LN_DP_H_RSTB_OEN",
    "LN_DP_S_RSTB",
    "LN_H_RSTB",
    "LN_RX_DP_S_RSTB",
    "LN_RX_H_PWRDN",
    "LN_RX_S_CLKGATE_FRC_ON",
    "LN_RX_S_COMCLK_FRC_ON",
    "LN_RX_S_COMCLK_SEL",
    "LN_RX_S_PWRDN",
    "LN_RX_S_RSTB",
    "LN_S_RSTB",
    "LN_TX_DP_S_RSTB",
    "LN_TX_H_PWRDN",
    "LN_TX_S_PWRDN",
    "LN_TX_S_RSTB",
    "LOCAL_FAULT",
    "LOCAL_FAULT_LH",
    "LOCAL_PCS_LOOPBACK_ENABLE",
    "LOGICAL0_TO_PHY_SEL",
    "LOGICAL1_TO_PHY_SEL",
    "LOGICAL2_TO_PHY_SEL",
    "LOGICAL3_TO_PHY_SEL",
    "LOOPCNT0",
    "LOOPCNT0_OEN",
    "LOOPCNT1",
    "LOOPCNT1_OEN",
    "LOST_PLL_LOCK_SM",
    "LOS_FILTER_COUNT",
    "LOS_THRESH",
    "LPI_EN",
    "LPI_ENABLE",
    "LPI_RECEIVED",
    "LPI_RECEIVED_LH",
    "LP_BASE1",
    "LP_BASE2",
    "LP_BASE3",
    "LP_OUI_UP1",
    "LP_OUI_UP2",
    "LP_OUI_UP3",
    "LP_OUI_UP4",
    "LP_OUI_UP5",
    "LP_PAGE_0",
    "LP_PAGE_1",
    "LP_PAGE_2",
    "LP_PAGE_RDY",
    "LP_PAGE_RDY_EN",
    "LP_PAGE_RDY_INT",
    "LTXSM_STATE",
    "MAC_CREDITGENCNT",
    "MAC_CREDITGENCNT_OEN",
    "MASTER_PORT_NUM",
    "MAX_PRBS_BURST_ERR_LENGTH_STATUS",
    "MDIO_ADDR_DATA",
    "MDIO_AER",
    "MDIO_BLK_ADDR",
    "MDIO_BRCST_PORT_ADDR",
    "MDIO_DEVAD",
    "MDIO_DEV_AN_EN",
    "MDIO_DEV_CL22_EN",
    "MDIO_DEV_DTE_EN",
    "MDIO_DEV_PCS_EN",
    "MDIO_DEV_PHY_EN",
    "MDIO_DEV_PMD_EN",
    "MDIO_FUNCTION",
    "MDIO_MASKDATA",
    "MDIO_MULTI_MMDS_EN",
    "MDIO_MULTI_PRTS_EN",
    "MEASURE_LFSR_CNT",
    "MEASURE_TIMEOUT",
    "MEAS_INCOMPLETE",
    "MICRO_AUTOINC_RDADDR_EN",
    "MICRO_AUTOINC_WRADDR_EN",
    "MICRO_CODE_RAM_ECC_ADDRESS",
    "MICRO_CODE_RAM_TM",
    "MICRO_CORE_CLK_EN",
    "MICRO_CORE_RSTB",
    "MICRO_DR_LOOKTAB_EN",
    "MICRO_DR_SIZE",
    "MICRO_ECCG_MODE",
    "MICRO_ECC_CORRUPT",
    "MICRO_ECC_FRC_DISABLE",
    "MICRO_GEN_INTR_RMI_MBOX0WR",
    "MICRO_GEN_INTR_RMI_MBOX1WR",
    "MICRO_M0_DEFAULT_SLAVE_ERROR",
    "MICRO_M0_HRESP_EN",
    "MICRO_MASTER_CLK_EN",
    "MICRO_MASTER_RSTB",
    "MICRO_PRAMIF_AHB_WRADDR_LSW",
    "MICRO_PRAMIF_AHB_WRADDR_MSW",
    "MICRO_PRAMIF_EN",
    "MICRO_PRAM_IF_RSTB",
    "MICRO_PR_AUTOINC_NXT_WRADDR_LSW",
    "MICRO_PR_DEFAULT_SLAVE_ERROR",
    "MICRO_PVT_TEMPDATA_FRC",
    "MICRO_PVT_TEMPDATA_FRCVAL",
    "MICRO_PVT_TEMPDATA_RMI",
    "MICRO_RA_AUTOINC_NXT_RDADDR_LSW",
    "MICRO_RA_AUTOINC_NXT_WRADDR_LSW",
    "MICRO_RA_ECC_RDDATA",
    "MICRO_RA_ECC_WRDATA",
    "MICRO_RA_INIT",
    "MICRO_RA_INITDONE",
    "MICRO_RA_RDADDR_LSW",
    "MICRO_RA_RDADDR_MSW",
    "MICRO_RA_RDDATASIZE",
    "MICRO_RA_RDDATA_LSW",
    "MICRO_RA_RDDATA_MSW",
    "MICRO_RA_WRADDR_LSW",
    "MICRO_RA_WRADDR_MSW",
    "MICRO_RA_WRDATASIZE",
    "MICRO_RA_WRDATA_LSW",
    "MICRO_RA_WRDATA_MSW",
    "MICRO_RMI_DEFAULT_SLAVE_ERROR",
    "MICRO_RMI_ECC_CORR_ERR_INTR_EN",
    "MICRO_RMI_ECC_CORR_ERR_STATUS",
    "MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN",
    "MICRO_RMI_ECC_MULTIROW_ERR_STATUS",
    "MICRO_RMI_ECC_UNCORR_ERR_INTR_EN",
    "MICRO_RMI_ECC_UNCORR_ERR_STATUS",
    "MICRO_RMI_M0_LOCKUP_INTR_EN",
    "MICRO_RMI_M0_LOCKUP_STATUS",
    "MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN",
    "MICRO_RMI_M0_SYSTEMRESETREQ_STATUS",
    "MICRO_RMI_MBOX_MSGOUT_INTR_EN",
    "MICRO_RMI_MBOX_MSGOUT_STATUS",
    "MICRO_RMI_MBOX_SEND_MSGIN",
    "MICRO_RMI_TO_MICRO_MBOX0",
    "MICRO_RMI_TO_MICRO_MBOX1",
    "MICRO_SW_PMI_HP_EXT_RSTB",
    "MICRO_SW_PMI_HP_RSTB",
    "MICRO_TO_RMI_MBOX0",
    "MICRO_TO_RMI_MBOX1",
    "MICRO_TX_DISABLE",
    "MODEL_NUMBER",
    "MSA_25G_5BIT_XOR",
    "MSA_25G_AM0_FORMAT",
    "MSA_25G_AM123_FORMAT",
    "MSA_25G_AM_EN",
    "MSA_25G_CWSCR_EN",
    "MSA_50G_AM0_FORMAT",
    "MSA_50G_AM123_FORMAT",
    "MSA_COUNT_SEL",
    "MSA_IEEE_DET_EN",
    "MSA_IEEE_DET_STATE",
    "MSA_IEEE_DET_TIMEPERIOD",
    "MSA_WINDOW_SEL",
    "MULTIPRTS_EN",
    "NEXT_PAGE",
    "NEXT_PAGE_WAIT",
    "NUMBER_PKT",
    "NUM_ADVERTISED_LANES",
    "NUM_LANES",
    "NUM_LANES_OEN",
    "NUM_LANES_OVERRIDE_VALUE",
    "ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_0",
    "ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_1",
    "ONE_BIT_ERR_EVENT_CL91_BUFFER_BLK_2",
    "ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_HI",
    "ONE_BIT_ERR_EVENT_CL91_FEC_RAM1_LO",
    "ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_HI",
    "ONE_BIT_ERR_EVENT_CL91_FEC_RAM2_LO",
    "ONE_BIT_ERR_EVENT_DESKEW_0",
    "ONE_BIT_ERR_EVENT_DESKEW_1",
    "ONE_BIT_ERR_EVENT_DESKEW_2",
    "ONE_BIT_ERR_EVENT_FEC_0",
    "ONE_BIT_ERR_EVENT_FEC_1",
    "ONE_BIT_ERR_EVENT_FEC_2",
    "ONE_BIT_ERR_EVENT_FEC_3",
    "OSR_MODE",
    "OSR_MODE_FRC",
    "OSR_MODE_FRC_VAL",
    "OSR_MODE_OEN",
    "OSR_MODE_PIN",
    "OS_ALL_EDGES",
    "OS_MODE",
    "OS_MODE_OEN",
    "OS_PATTERN_ENHANCED",
    "OUI_LOWER_DATA",
    "OUI_UPPER_DATA",
    "PAGE_TOO_LONG",
    "PAGE_TOO_SHORT",
    "PATT_GEN_EN",
    "PATT_GEN_SEQ_0",
    "PATT_GEN_SEQ_1",
    "PATT_GEN_SEQ_10",
    "PATT_GEN_SEQ_11",
    "PATT_GEN_SEQ_12",
    "PATT_GEN_SEQ_13",
    "PATT_GEN_SEQ_14",
    "PATT_GEN_SEQ_2",
    "PATT_GEN_SEQ_3",
    "PATT_GEN_SEQ_4",
    "PATT_GEN_SEQ_5",
    "PATT_GEN_SEQ_6",
    "PATT_GEN_SEQ_7",
    "PATT_GEN_SEQ_8",
    "PATT_GEN_SEQ_9",
    "PATT_GEN_START_POS",
    "PATT_GEN_STOP_POS",
    "PAYLOAD_TYPE",
    "PCS_XS",
    "PD_CL37_COMPLETED",
    "PD_COMPLETED",
    "PD_DME_LOCK_TIMER_PERIOD",
    "PD_IN_PROGRESS",
    "PD_KX_EN",
    "PD_SD_TIMER_PERIOD",
    "PHASE_ERR_OFFSET",
    "PHASE_ERR_OFFSET_EN",
    "PHS_SUM_IGNORE_DSC_LOCK",
    "PHY_XS",
    "PIPELINE_RESET_COUNT",
    "PKTGEN_EN",
    "PKT_SIZE",
    "PLL_FORCE_CAP_DONE",
    "PLL_FORCE_CAP_DONE_EN",
    "PLL_FORCE_CAP_PASS",
    "PLL_FORCE_CAP_PASS_EN",
    "PLL_FORCE_FDONE",
    "PLL_FORCE_FDONE_EN",
    "PLL_FORCE_FPASS",
    "PLL_LOCK",
    "PLL_LOCK_FRC",
    "PLL_LOCK_FRC_VAL",
    "PLL_LOCK_LH_LL",
    "PLL_LOCK_OVRD",
    "PLL_LOCK_STS",
    "PLL_LOCK_TIMED_OUT",
    "PLL_LOCK_TIMER_PERIOD",
    "PLL_MODE",
    "PLL_RESET_EN",
    "PLL_SEQ_DONE",
    "PLL_SEQ_DONE_LH_LL",
    "PLL_SEQ_PASS",
    "PLL_SEQ_PASS_LH_LL",
    "PLL_SEQ_START",
    "PMA_PMD",
    "PMD_CORE_DP_H_RSTB_PKILL",
    "PMD_CORE_MODE",
    "PMD_LANE_MODE",
    "PMD_LN_DP_H_RSTB_PKILL",
    "PMD_LN_H_RSTB_PKILL",
    "PMD_LN_RX_H_PWRDN_PKILL",
    "PMD_LN_TX_H_PWRDN_PKILL",
    "PMD_LOCK_TIMED_OUT",
    "PMD_LOCK_TIMER_PERIOD",
    "PMD_MDIO_TRANS_PKILL",
    "PMD_RX_CLK_VLD_FRC",
    "PMD_RX_CLK_VLD_FRC_VAL",
    "PMD_RX_LOCK",
    "PMD_RX_LOCK_CHANGE",
    "PMD_TX_CLK_VLD_FRC",
    "PMD_TX_CLK_VLD_FRC_VAL",
    "PMD_TX_DISABLE_PKILL",
    "PORT_MODE_SEL",
    "POR_H_RSTB",
    "PRBS_BURST_ERR_LENGTH_STATUS",
    "PRBS_BURST_LEN_CHK_EN",
    "PRBS_CHK_CLK_EN_FRC_ON",
    "PRBS_CHK_EN",
    "PRBS_CHK_EN_AUTO_MODE",
    "PRBS_CHK_EN_TIMEOUT",
    "PRBS_CHK_EN_TIMER_MODE",
    "PRBS_CHK_ERR_CNT_BURST_MODE",
    "PRBS_CHK_ERR_CNT_LSB",
    "PRBS_CHK_ERR_CNT_MSB",
    "PRBS_CHK_INV",
    "PRBS_CHK_LOCK",
    "PRBS_CHK_LOCK_CNT",
    "PRBS_CHK_LOCK_LOST_LH",
    "PRBS_CHK_MODE",
    "PRBS_CHK_MODE_SEL",
    "PRBS_CHK_OOL_CNT",
    "PRBS_GEN_EN",
    "PRBS_GEN_ERR_INS",
    "PRBS_GEN_INV",
    "PRBS_GEN_MODE_SEL",
    "PRESET_DSC_AFE_BANK",
    "PRESET_DSC_A_BANK",
    "PRESET_DSC_C_BANK",
    "PRESET_DSC_D_BANK",
    "PRE_FREQ_DET_TIME",
    "PRTAD_BCST",
    "PRTP_DATA_PATTERN_SEL",
    "PRTP_ERR_COUNT",
    "PRTP_LOCK",
    "PSLL0_TO_VL_MAPPING",
    "PSLL1_TO_VL_MAPPING",
    "PSLL2_TO_VL_MAPPING",
    "PSLL3_TO_VL_MAPPING",
    "PSLL4_TO_VL_MAPPING",
    "PULSE_TOO_LONG",
    "PULSE_TOO_MODERATE",
    "PULSE_TOO_SHORT",
    "PWRDN_SEQ_TIMER",
    "REFCLK_DIVCNT",
    "REFCLK_DIVCNT_SEL",
    "REFCLK_SEL",
    "REGID1",
    "REGID2",
    "REMOTE_FAULT",
    "REMOTE_FAULT_LH",
    "REMOTE_FAULT_SET",
    "REMOTE_PCS_LOOPBACK_ENABLE",
    "RESCAL_FRC",
    "RESCAL_FRC_VAL",
    "RESCAL_IN",
    "RESOLUTION_ERROR",
    "RESOLVED_25_MODE",
    "RESOLVED_PORT_MODE",
    "RESTART_LOCK_LH",
    "RESTART_LOCK_LIVE",
    "RESTART_LOCK_LL",
    "RESTART_PI_EXT_MODE",
    "RESTART_PMD_RESTART",
    "RESTART_SIGDET",
    "RES_CAL_CNTR",
    "RETRY_TIME",
    "REVID2",
    "REVID_BONDING",
    "REVID_CL72",
    "REVID_EEE",
    "REVID_LLP",
    "REVID_MDIO",
    "REVID_MICRO",
    "REVID_MODEL",
    "REVID_MULTIPLICITY",
    "REVID_PIR",
    "REVID_PROCESS",
    "REVID_REV_LETTER",
    "REVID_REV_NUMBER",
    "REV_LETTER",
    "REV_NUMBER",
    "RF_MEM_TM",
    "RMT_LPBK_EN",
    "RMT_LPBK_PD_EARLY_IND",
    "RMT_LPBK_PD_FRC_ON",
    "RMT_LPBK_PD_LATE_IND",
    "RMT_LPBK_PD_MODE",
    "RSTB_LANE",
    "RSTB_TX_LANE",
    "RST_SEQ_DIS_FLT_MODE",
    "RST_SEQ_TIMER",
    "RS_FEC_REQ_EN",
    "RS_FEC_REQ_SEL",
    "RXA_DFE_TAP10",
    "RXA_DFE_TAP10_MUX",
    "RXA_DFE_TAP11",
    "RXA_DFE_TAP11_MUX",
    "RXA_DFE_TAP12",
    "RXA_DFE_TAP12_MUX",
    "RXA_DFE_TAP13",
    "RXA_DFE_TAP13_MUX",
    "RXA_DFE_TAP14",
    "RXA_DFE_TAP14_MUX",
    "RXA_DFE_TAP2",
    "RXA_DFE_TAP3",
    "RXA_DFE_TAP4",
    "RXA_DFE_TAP5",
    "RXA_DFE_TAP6",
    "RXA_DFE_TAP7",
    "RXA_DFE_TAP7_MUX",
    "RXA_DFE_TAP8",
    "RXA_DFE_TAP8_MUX",
    "RXA_DFE_TAP9",
    "RXA_DFE_TAP9_MUX",
    "RXA_SLICER_OFFSET_ADJ_DN",
    "RXA_SLICER_OFFSET_ADJ_DP",
    "RXA_SLICER_OFFSET_ADJ_LMS",
    "RXA_SLICER_OFFSET_ADJ_ZN",
    "RXA_SLICER_OFFSET_ADJ_ZP",
    "RXB_DFE_TAP10",
    "RXB_DFE_TAP10_MUX",
    "RXB_DFE_TAP11",
    "RXB_DFE_TAP11_MUX",
    "RXB_DFE_TAP12",
    "RXB_DFE_TAP12_MUX",
    "RXB_DFE_TAP13",
    "RXB_DFE_TAP13_MUX",
    "RXB_DFE_TAP14",
    "RXB_DFE_TAP14_MUX",
    "RXB_DFE_TAP2",
    "RXB_DFE_TAP3",
    "RXB_DFE_TAP4",
    "RXB_DFE_TAP5",
    "RXB_DFE_TAP6",
    "RXB_DFE_TAP7",
    "RXB_DFE_TAP7_MUX",
    "RXB_DFE_TAP8",
    "RXB_DFE_TAP8_MUX",
    "RXB_DFE_TAP9",
    "RXB_DFE_TAP9_MUX",
    "RXB_SLICER_OFFSET_ADJ_DN",
    "RXB_SLICER_OFFSET_ADJ_DP",
    "RXB_SLICER_OFFSET_ADJ_LMS",
    "RXB_SLICER_OFFSET_ADJ_ZN",
    "RXB_SLICER_OFFSET_ADJ_ZP",
    "RXC_DFE_TAP10",
    "RXC_DFE_TAP10_MUX",
    "RXC_DFE_TAP11",
    "RXC_DFE_TAP11_MUX",
    "RXC_DFE_TAP12",
    "RXC_DFE_TAP12_MUX",
    "RXC_DFE_TAP13",
    "RXC_DFE_TAP13_MUX",
    "RXC_DFE_TAP14",
    "RXC_DFE_TAP14_MUX",
    "RXC_DFE_TAP2",
    "RXC_DFE_TAP3",
    "RXC_DFE_TAP4",
    "RXC_DFE_TAP5",
    "RXC_DFE_TAP6",
    "RXC_DFE_TAP7",
    "RXC_DFE_TAP7_MUX",
    "RXC_DFE_TAP8",
    "RXC_DFE_TAP8_MUX",
    "RXC_DFE_TAP9",
    "RXC_DFE_TAP9_MUX",
    "RXC_SLICER_OFFSET_ADJ_DN",
    "RXC_SLICER_OFFSET_ADJ_DP",
    "RXC_SLICER_OFFSET_ADJ_LMS",
    "RXC_SLICER_OFFSET_ADJ_ZN",
    "RXC_SLICER_OFFSET_ADJ_ZP",
    "RXD_DFE_TAP10",
    "RXD_DFE_TAP10_MUX",
    "RXD_DFE_TAP11",
    "RXD_DFE_TAP11_MUX",
    "RXD_DFE_TAP12",
    "RXD_DFE_TAP12_MUX",
    "RXD_DFE_TAP13",
    "RXD_DFE_TAP13_MUX",
    "RXD_DFE_TAP14",
    "RXD_DFE_TAP14_MUX",
    "RXD_DFE_TAP2",
    "RXD_DFE_TAP3",
    "RXD_DFE_TAP4",
    "RXD_DFE_TAP5",
    "RXD_DFE_TAP6",
    "RXD_DFE_TAP7",
    "RXD_DFE_TAP7_MUX",
    "RXD_DFE_TAP8",
    "RXD_DFE_TAP8_MUX",
    "RXD_DFE_TAP9",
    "RXD_DFE_TAP9_MUX",
    "RXD_SLICER_OFFSET_ADJ_DN",
    "RXD_SLICER_OFFSET_ADJ_DP",
    "RXD_SLICER_OFFSET_ADJ_LMS",
    "RXD_SLICER_OFFSET_ADJ_ZN",
    "RXD_SLICER_OFFSET_ADJ_ZP",
    "RXFIFO_EMPTY",
    "RXFIFO_FULL",
    "RXFIFO_OVERRUN",
    "RXFIFO_UNDERRUN",
    "RXPKTCNT_L",
    "RXPKTCNT_U",
    "RX_BP",
    "RX_CLK_VLD_LH",
    "RX_CLK_VLD_LIVE",
    "RX_CLK_VLD_LL",
    "RX_CLK_VLD_OVRD",
    "RX_CLK_VLD_STS",
    "RX_DATA_15_TO_0",
    "RX_DATA_35_TO_20",
    "RX_DATA_THRESH_SEL",
    "RX_DSC_LOCK",
    "RX_DSC_LOCK_FRC",
    "RX_DSC_LOCK_FRC_VAL",
    "RX_INVALID_SEQ",
    "RX_LMS_THRESH_SEL",
    "RX_LOCK_LH",
    "RX_LOCK_LIVE",
    "RX_LOCK_LL",
    "RX_LOCK_OVRD",
    "RX_LOCK_STS",
    "RX_MODE",
    "RX_MP_MISMATCH",
    "RX_MP_NULL",
    "RX_MP_OUI",
    "RX_MSBUS_TYPE",
    "RX_NP",
    "RX_NP_TOGGLE_ERR",
    "RX_PF2_CTRL",
    "RX_PF_CTRL",
    "RX_PHASE_THRESH_SEL",
    "RX_PI_CNT_BIN_D",
    "RX_PI_CNT_BIN_DQ",
    "RX_PI_CNT_BIN_D_LD",
    "RX_PI_CNT_BIN_D_PD",
    "RX_PI_CNT_BIN_L",
    "RX_PI_CNT_BIN_LQ",
    "RX_PI_CNT_BIN_L_LD",
    "RX_PI_CNT_BIN_P",
    "RX_PI_CNT_BIN_PQ",
    "RX_PI_CNT_BIN_P_PD",
    "RX_PI_MANUAL_MODE",
    "RX_PI_MANUAL_STROBE",
    "RX_PI_PHASE_STEP_CNT",
    "RX_PI_PHASE_STEP_DIR",
    "RX_PI_SLICERS_EN",
    "RX_PKT_CHECK_EN",
    "RX_PMD_DP_INVERT",
    "RX_PORT_SEL",
    "RX_PRTP_EN",
    "RX_RESTART_PMD",
    "RX_RESTART_PMD_HOLD",
    "RX_UNEXPECTED_PAGE",
    "RX_UP_OUI_MATCH",
    "RX_UP_OUI_MISMATCH",
    "RX_VGA_CTRL",
    "RX_VGA_CTRL_VAL",
    "R_CL91_CW_SCRAMBLE",
    "R_CL91_CW_SCRAMBLE_OEN",
    "R_CL91_FEC_MODE",
    "R_FEC_ENABLE",
    "R_FIVE_BIT_XOR_EN",
    "R_FIVE_BIT_XOR_EN_OEN",
    "R_HG2_ENABLE",
    "R_HG2_ENABLE_OEN",
    "R_MERGE_MODE",
    "R_MERGE_MODE_OEN",
    "R_TC_IN_MODE",
    "R_TC_IN_MODE_OEN",
    "R_TC_MODE",
    "R_TC_MODE_OEN",
    "R_TC_OUT_MODE",
    "R_TC_OUT_MODE_OEN",
    "R_TEST_MODE_CFG",
    "R_TYPE_CODED",
    "SCR_MODE",
    "SCR_MODE_OEN",
    "SC_BYPASS",
    "SC_FSM_STATUS",
    "SC_IGNORE_TX_DATA_VLD",
    "SDK_TX_DISABLE",
    "SEEDA0",
    "SEEDA1",
    "SEEDA2",
    "SEEDA3",
    "SEEDB0",
    "SEEDB1",
    "SEEDB2",
    "SEEDB3",
    "SEND_ACK",
    "SET_BER_WINDOW_512",
    "SET_MEAS_INCOMPLETE",
    "SET_SYMB_ERR_WINDOW_128",
    "SIGDET_DP_RSTB_EN",
    "SIGNAL_DETECT",
    "SIGNAL_DETECT_CHANGE",
    "SIGNAL_DETECT_FILTER_1US",
    "SIGNAL_DETECT_FILTER_COUNT",
    "SIGNAL_DETECT_FRC",
    "SIGNAL_DETECT_FRC_VAL",
    "SIGNAL_DETECT_LH",
    "SIGNAL_DETECT_LIVE",
    "SIGNAL_DETECT_LL",
    "SIGNAL_DETECT_OVRD",
    "SIGNAL_DETECT_RAW",
    "SIGNAL_DETECT_RAW_CHANGE",
    "SIGNAL_DETECT_STS",
    "SIGNAL_DETECT_THRESH",
    "SINGLE_PORT_MODE",
    "SLOWDN_XOR",
    "SOFT_RST_RX",
    "SOFT_RST_TX",
    "SPARE0",
    "SPARE1",
    "SPEED",
    "SPEED_FORCE",
    "SRF_MEM_TM",
    "STAND_ALONE_MODE",
    "SUP_RST_SEQ_FRC",
    "SUP_RST_SEQ_FRC_VAL",
    "SW_AN_BP_0",
    "SW_AN_BP_1",
    "SW_AN_BP_2",
    "SW_SPEED_CHANGE",
    "SW_SPEED_CHANGE_DONE",
    "SW_SPEED_CONFIG_VLD",
    "SYMBOL_ERROR_TMR_PERIOD",
    "SYMBOL_ERR_CNT_THRESHOLD",
    "SYNCE_FRACTIONAL_DIVSOR_CFG",
    "SYNCE_MODE_PHY_LANE0",
    "SYNCE_MODE_PHY_LANE1",
    "SYNCE_MODE_PHY_LANE2",
    "SYNCE_MODE_PHY_LANE3",
    "SYNCE_STAGE0_MODE_PHY_LANE0",
    "SYNCE_STAGE0_MODE_PHY_LANE1",
    "SYNCE_STAGE0_MODE_PHY_LANE2",
    "SYNCE_STAGE0_MODE_PHY_LANE3",
    "TC",
    "TDT_BIT_SEL",
    "TDT_CYCLE_BIN",
    "TDT_CYCLE_SEL",
    "TDT_PRBS_MODE",
    "TDT_PRBS_SLIP",
    "TDT_TRNSUM_EN",
    "TECH_PROC",
    "THRESH_STEP_SIZE",
    "THRESH_TIMER_T1",
    "TICK_DENOMINATOR",
    "TICK_NUMERATOR_LOWER",
    "TICK_NUMERATOR_UPPER",
    "TICK_OVERRIDE",
    "TIMEOUT_COUNT",
    "TIMEOUT_ERROR",
    "TIMER_DONE_FRC",
    "TIMER_DONE_FRC_VAL",
    "TLA_LN_SEQUENCER_FSM_STATUS1",
    "TLA_SEQ_FSM_STATUS",
    "TLB_RX_DIFF_DEC_EN",
    "TLB_TX_DIFF_ENC_EN",
    "TRANSMIT_DISABLE",
    "TRNSUM",
    "TRNSUM_A",
    "TRNSUM_A_LOW",
    "TRNSUM_B",
    "TRNSUM_B_LOW",
    "TRNSUM_C",
    "TRNSUM_CLR_FRC",
    "TRNSUM_CLR_FRC_VAL",
    "TRNSUM_COR_SEL",
    "TRNSUM_C_LOW",
    "TRNSUM_D",
    "TRNSUM_D_LOW",
    "TRNSUM_EDGE_PATTERN_EN",
    "TRNSUM_EN",
    "TRNSUM_ERROR_COUNT_EN",
    "TRNSUM_EYE_CLOSURE_EN",
    "TRNSUM_FRZ_FRC",
    "TRNSUM_FRZ_FRC_VAL",
    "TRNSUM_GAIN",
    "TRNSUM_INV_PATTERN_EN",
    "TRNSUM_LOW",
    "TRNSUM_PATTERN",
    "TRNSUM_PATTERN_BIT_EN",
    "TRNSUM_PATTERN_FULL_CHECK_OFF",
    "TRNSUM_QPHASE_MULT_EN",
    "TRNSUM_RANDOM_TAPSEL_DISABLE",
    "TRNSUM_SEL_EMUX",
    "TRNSUM_TAP_EN",
    "TRNSUM_TAP_RANGE_SEL",
    "TRNSUM_TAP_SIGN",
    "TSC_CLK_CTRL",
    "TSC_CREDIT_SEL",
    "TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_0",
    "TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_1",
    "TWO_BIT_ERR_EVENT_CL91_BUFFER_BLK_2",
    "TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_HI",
    "TWO_BIT_ERR_EVENT_CL91_FEC_RAM1_LO",
    "TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_HI",
    "TWO_BIT_ERR_EVENT_CL91_FEC_RAM2_LO",
    "TWO_BIT_ERR_EVENT_DESKEW_0",
    "TWO_BIT_ERR_EVENT_DESKEW_1",
    "TWO_BIT_ERR_EVENT_DESKEW_2",
    "TWO_BIT_ERR_EVENT_FEC_0",
    "TWO_BIT_ERR_EVENT_FEC_1",
    "TWO_BIT_ERR_EVENT_FEC_2",
    "TWO_BIT_ERR_EVENT_FEC_3",
    "TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD",
    "TXCOM_CL93N72_WAIT_CNTR_LIMIT",
    "TXCOM_MAIN_TAP_ALERT_VAL",
    "TXCOM_POST_TAP_ALERT_VAL",
    "TXCOM_PRE_TAP_ALERT_VAL",
    "TXFIFO_EMPTY",
    "TXFIFO_FULL",
    "TXFIFO_OVERRUN",
    "TXFIFO_UNDERRUN",
    "TXFIR_MAIN_ADJUSTED",
    "TXFIR_MAIN_AFTER_OVR",
    "TXFIR_MAIN_OFFSET",
    "TXFIR_POST2",
    "TXFIR_POST2_ADJUSTED",
    "TXFIR_POST2_OFFSET",
    "TXFIR_POST3",
    "TXFIR_POST3_ADJUSTED",
    "TXFIR_POST3_OFFSET",
    "TXFIR_POST_ADJUSTED",
    "TXFIR_POST_AFTER_OVR",
    "TXFIR_POST_OFFSET",
    "TXFIR_PRE_ADJUSTED",
    "TXFIR_PRE_AFTER_OVR",
    "TXFIR_PRE_OFFSET",
    "TXPKTCNT_L",
    "TXPKTCNT_U",
    "TXSM_STATE",
    "TX_CLK_VLD_OVRD",
    "TX_CLK_VLD_STS",
    "TX_DISABLE",
    "TX_DISABLE_OEN",
    "TX_DISABLE_OUTPUT_SEL",
    "TX_DISABLE_TIMER_CTRL",
    "TX_EEE_ALERT_EN",
    "TX_EEE_QUIET_EN",
    "TX_LANE_MAP_0",
    "TX_LANE_MAP_1",
    "TX_LANE_MAP_2",
    "TX_LANE_MAP_3",
    "TX_LINK_INTERRUPT",
    "TX_LOCAL_FAULT",
    "TX_LPI_RECEIVED",
    "TX_MODE",
    "TX_MSBUS_TYPE",
    "TX_MUX_SEL_ORDER",
    "TX_NONCE",
    "TX_PCS_NATIVE_ANA_FRMT_EN",
    "TX_PI_EN",
    "TX_PI_EXT_CTRL_EN",
    "TX_PI_EXT_PHASE_BWSEL_INTEG",
    "TX_PI_FIRST_ORDER_BWSEL_INTEG",
    "TX_PI_FREQ_OVERRIDE_EN",
    "TX_PI_FREQ_OVERRIDE_VAL",
    "TX_PI_FRZ_FRC",
    "TX_PI_FRZ_FRC_VAL",
    "TX_PI_FRZ_MODE",
    "TX_PI_INTEG1_REG",
    "TX_PI_INTEG2_REG",
    "TX_PI_JITTER_FILTER_EN",
    "TX_PI_JIT_AMP",
    "TX_PI_JIT_FREQ_IDX",
    "TX_PI_JIT_SSC_FREQ_MODE",
    "TX_PI_LOOP_FILTER_STABLE",
    "TX_PI_LOOP_TIMING_SRC_SEL",
    "TX_PI_PHASE_CNTR",
    "TX_PI_PHASE_ERR",
    "TX_PI_PHASE_INVERT",
    "TX_PI_PHASE_OVERRIDE",
    "TX_PI_PHASE_STEP_DIR",
    "TX_PI_PHASE_STEP_NUM",
    "TX_PI_PHASE_STROBE",
    "TX_PI_RESET_CODE_DBG",
    "TX_PI_RMT_LPBK_BYPASS_FLT",
    "TX_PI_SECOND_ORDER_BWSEL_INTEG",
    "TX_PI_SECOND_ORDER_LOOP_EN",
    "TX_PI_SJ_GEN_EN",
    "TX_PI_SSC_GEN_EN",
    "TX_PMD_DP_INVERT",
    "TX_PRTP_EN",
    "TX_REMOTE_FAULT",
    "TX_RESET_COUNT",
    "TX_S_CLKGATE_FRC_ON",
    "TX_S_COMCLK_FRC_ON",
    "TX_S_COMCLK_SEL",
    "TX_TEST_MODE_CFG",
    "TX_TEST_PORT_SEL",
    "T_CL91_CW_SCRAMBLE",
    "T_CL91_CW_SCRAMBLE_OEN",
    "T_CL91_FEC_MODE",
    "T_ENC_MODE",
    "T_ENC_MODE_OEN",
    "T_FEC_ENABLE",
    "T_FIFO_MODE",
    "T_FIFO_MODE_OEN",
    "T_FIVE_BIT_XOR_EN",
    "T_FIVE_BIT_XOR_EN_OEN",
    "T_HG2_ENABLE",
    "T_HG2_ENABLE_OEN",
    "T_PMA_40B_MODE",
    "T_PMA_40B_MODE_OEN",
    "T_PMA_BITMUX_DELAY",
    "T_PMA_BITMUX_DELAY_OEN",
    "T_PMA_BTMX_MODE",
    "T_PMA_BTMX_MODE_OEN",
    "T_PMA_CL91_MUX_SEL",
    "T_PMA_CL91_MUX_SEL_OEN",
    "T_PMA_WATERMARK",
    "T_PMA_WATERMARK_OEN",
    "T_TC_OUT_OVERFLOW",
    "T_TC_OUT_UNDERFLOW",
    "T_TYPE_CODED",
    "UC_ACK_CORE_CFG_DONE",
    "UC_ACK_CORE_DP_RESET",
    "UC_ACK_DSC_CONFIG",
    "UC_ACK_DSC_EEE_DONE",
    "UC_ACK_DSC_RESTART",
    "UC_ACK_LANE_CFG_DONE",
    "UC_ACK_LANE_DP_RESET",
    "UC_ACTIVE",
    "UC_DSC_ERROR_FOUND",
    "UC_DSC_GP_UC_REQ",
    "UC_DSC_READY_FOR_CMD",
    "UC_DSC_SCRATCH",
    "UC_DSC_SUPP_INFO",
    "UC_TRNSUM_EN",
    "UC_TUNE_EN",
    "UNCORCOUNTH_STREAM0",
    "UNCORCOUNTH_STREAM1",
    "UNCORCOUNTH_STREAM2",
    "UNCORCOUNTH_STREAM3",
    "UNCORCOUNTH_STREAM4",
    "UNCORCOUNTL_STREAM0",
    "UNCORCOUNTL_STREAM1",
    "UNCORCOUNTL_STREAM2",
    "UNCORCOUNTL_STREAM3",
    "UNCORCOUNTL_STREAM4",
    "USE_100G_AM0",
    "USE_100G_AM123",
    "VCO_DONE_EN",
    "VCO_RANGE_ADJUST",
    "VCO_RST_EN",
    "VCO_START_TIME",
    "VCO_STEP_TIME",
    "VGA_DEC",
    "VGA_INC",
    "VGA_TIMER_T2",
    "VGA_WRITE",
    "WAIT_FOR_ACK_EN",
    "WIN_CAL_CNTR",
    "WIS",
    "WM",
};

#endif
#endif
#endif
#endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */



/*******************************************************************************
 *
 * The following is the symbol table itself. 
 * It defines the entries for all registers and memories.
 * It also incorporates the field information for each register and memory if
 * applicable.
 */
static const phymod_symbol_t bcmi_tscf_xgxs_gen2_syms[] = {
#ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_TSCF_XGXS
{
	BCMI_TSCF_XGXS_PHYID2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PHYID2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PHYID2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL22_B0_PHYID2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x600d, /* 24589 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PHYID3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PHYID3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PHYID3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL22_B0_PHYID3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8770, /* 34672 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_SETUP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_SETUP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_SETUP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_SETUP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x180, /* 384 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_SYNCE_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_SYNCE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xaa, /* 170 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_SYNCE_CTL_STAGE0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_SYNCE_CTL_STAGE0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_SYNCE_CONTROL_STAGE0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_SPD_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_SPD_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_SPD_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_SPEED_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_DEVINPKG5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_DEVINPKG5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_DEVINPKG5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_DEVICEINPKG5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x83, /* 131 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_TICK_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_TICK_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_TICK_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_TICK_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_TICK_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_TICK_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_TICK_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_TICK_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_LPBK_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_LPBK_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_LPBK_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_LOOPBACK_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_MDIO_BCST_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_MDIO_BCST_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_MDIO_BCST_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_MDIO_BROADCAST",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xf800, /* 63488 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0ACC_TMOUT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_REGACCESS_TIMEOUT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x50, /* 80 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0ACC_TMOUT_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0ACC_TMOUT_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_REGACCESS_TIMEOUT_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MAIN0_SERDESID_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MAIN0_SERDESID_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MAIN0_SERDESID_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MAIN0_SERDESID",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2d5, /* 725 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X1_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X1_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X1_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X1_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X1_MODE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X1_MODE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X1_MODE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X1_MODE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X1_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X1_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X1_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X1_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X1_OVRR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X1_OVRR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X1_OVRR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X1_OVERRIDE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PKTGENCTRL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_CTL2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_CTL2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_CTL2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PKTGENCTRL2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x28, /* 40 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_CTL3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_CTL3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_CTL3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PKTGENCTRL3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PRTPCTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PRTPCTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PRTPCTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PRTPCONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_CRCERRCNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_CRCERRCNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_CRCERRCNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_CRCERRORCOUNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDA0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDA0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDA1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDA1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDA2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDA2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDA3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDA3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDA3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDB0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDB0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDB1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDB1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDB2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDB2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PCS_SEEDB3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PCS_SEEDB3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN0_PCS_SEEDB3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTES_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_PAYLOADBYTES_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_PAYLOADBYTES_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_PAYLOADBYTES",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERRMASK4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERRORMASK4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERRMASK3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERRORMASK3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERRMASK2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERRORMASK2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERRMASK1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERRORMASK1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERRMASK0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERRMASK0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERRORMASK0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERR_INJ_EN0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERR_INJ_EN0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PKTGEN_ERR_INJ_EN1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PKTGEN_ERR_INJ_EN1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PKTGEN1_ERR_INJ_EN1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_AM_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_AM_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_AM_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_SHARED_CL82_AM_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4000, /* 16384 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_LN_0_AM_BYTE10_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_LN_0_AM_BYTE10_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_AM_REGS_LANE_0_AM_BYTE10",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7690, /* 30352 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_LN_1_AM_BYTE10_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_LN_1_AM_BYTE10_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_AM_REGS_LANE_1_AM_BYTE10",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc4f0, /* 50416 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_LANES_1_0_AM_BYTE2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_LANES_1_0_AM_BYTE2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_AM_REGS_LANES_1_0_AM_BYTE2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xe647, /* 58951 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X1_TX_LN_SWP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X1_TX_LN_SWP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X1_TX_LN_SWP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X1_CONTROL0_TX_LANE_SWAP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xe4, /* 228 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_DEC_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_DEC_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_DEC_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_DECODE_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x6140, /* 24896 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_DESKEW_WINS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_DESKEW_WINDOWS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4a6, /* 1190 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_CL91_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_CL91_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_CL91_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_CL91_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_DESKEW_WINS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_DESKEW_WINS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_DESKEW_WINDOWS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x54, /* 84 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_RX_LN_SWP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_RX_LN_SWP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_RX_LANE_SWAP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xe4, /* 228 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_SRF_MEM_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_SRF_MEM_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_SRF_MEM_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_SRF_MEM_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_RF_MEM_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_RF_MEM_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_RF_MEM_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_CONTROL0_RF_MEM_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_STS_FEC_MEM_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_STATUS_FEC_MEM_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_STS_FEC_MEM_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_STATUS_FEC_MEM_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_STS_FEC_MEM_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_STATUS_FEC_MEM_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_STS_FEC_MEM_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_STS_FEC_MEM_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_STATUS_FEC_MEM_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_1BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_INTR_STS_1BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_INTERRUPT_STATUS_1BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_STS_2BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_INTR_STS_2BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_INTERRUPT_STATUS_2BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_1BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_INTR_EN_1BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_INTERRUPT_EN_1BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff, /* 255 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_INTR_EN_2BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_INTR_EN_2BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_INTERRUPT_EN_2BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff, /* 255 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEM_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_DIS_ECC_MEM_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_DIS_ECC_MEM_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_DISABLE_ECC_MEM",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPT_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_ECC_CORRUPT_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_ECC_CORRUPT_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_ECC_CORRUPT_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_OUI_UPR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_OUI_UPR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_OUI_UPR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_OUI_UPPER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_OUI_LWR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_OUI_LWR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_OUI_LWR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_OUI_LOWER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_BAM_SPD_PRI_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_BAM_SPEED_PRI_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_BAM_SPD_PRI_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_BAM_SPEED_PRI_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_BAM_SPD_PRI_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_BAM_SPEED_PRI_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_BAM_SPD_PRI_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_BAM_SPEED_PRI_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_BAM_SPD_PRI_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_BAM_SPD_PRI_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_BAM_SPEED_PRI_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_IEEE_SPD_PRI_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_IEEE_SPD_PRI_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_IEEE_SPD_PRI_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_CONTROL_IEEE_SPEED_PRI_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNK_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_CL73_BRK_LNK_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_CL73_BRK_LNK_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_CL73_BREAK_LINK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_CL73_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_CL73_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_CL73_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_CL73_ERROR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCK_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_CL73_DME_LOCK_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_CL73_DME_LOCK_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_CL73_DME_LOCK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_PD_SD_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_PD_SD_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_PD_SD_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_PD_SD_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_IGNORE_LNK_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_IGNORE_LNK_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_IGNORE_LINK_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_CL72_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_LNK_FAIL_INHBT_TMR_CL72_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_LNK_FAIL_INHBT_TMR_NOT_CL72_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_DME_PAGE_TMR_TYPE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_DME_PAGE_TMR_TYPE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_TIMERS_DME_PAGE_TIMER_TYPE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3b5f, /* 15199 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_PLL_LOCK_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_PLL_LOCK_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_CONTROL_PLL_LOCK_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_PMD_LOCK_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_PMD_LOCK_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_CONTROL_PMD_LOCK_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_PIPE_RST_CNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_PIPE_RST_CNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_CONTROL_PIPELINE_RESET_COUNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff, /* 255 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_TX_RST_CNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_TX_RST_CNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_TX_RST_CNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_CONTROL_TX_RESET_COUNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_CONTROL_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_SPD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_SPD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR0_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR0_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE0_OVERRIDE_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_SPD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_SPD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR1_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR1_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE1_OVERRIDE_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_SPD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_SPD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR2_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR2_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE2_OVERRIDE_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_SPD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_SPD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X1_SPD_OVRR3_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X1_SPD_OVRR3_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X1_SPEED_OVERRIDE3_OVERRIDE_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_LO_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_LO_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_STS_CL91_FEC_RAM1_LO_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_HI_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM1_HI_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_STS_CL91_FEC_RAM1_HI_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_LO_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_LO_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_STS_CL91_FEC_RAM2_LO_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_HI_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X1_STS_CL91_FEC_RAM2_HI_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X1_STS_CL91_FEC_RAM2_HI_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_GLB_INT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_GLB_INT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_GLB_INT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_SW_MGMT_GLB_INT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X1_GLB_MASK_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X1_GLB_MASK_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X1_GLB_MASK_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X1_SW_MGMT_GLB_MASK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X2_CL82_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X2_CL82_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X2_CL82_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X2_CONTROL0_CL82_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x70, /* 112 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X2_CL82_TX_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X2_STATUS0_CL82_TX_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X2_CL82_TX_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X2_CL82_TX_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X2_STATUS0_CL82_TX_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X2_MISC_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X2_MISC_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X2_MISC_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X2_CONTROL0_MISC_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X2_MISC_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X2_MISC_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X2_MISC_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X2_CONTROL0_MISC_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x203, /* 515 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X2_CL82_SCRIDLE_TEST_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X2_CL82_SCRIDLE_TEST_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X2_CL82_SCRIDLE_TEST_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X2_STATUS0_CL82_SCRIDLE_TEST_ERR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_RX_LIVE_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_RX_LIVE_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_RX_LIVE_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_RX_LIVE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2000, /* 8192 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_RX_LATCH_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_RX_LATCH_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_RX_LATCH_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_RX_LATCHED_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_BER_LO_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_BER_LO_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_BER_LO_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_BER_LO",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_BER_HO_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_BER_HO_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_BER_HO_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_BER_HO",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HO_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL82_ERRED_BLKS_HO_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL82_ERRED_BLKS_HO_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL82_ERRORED_BLOCKS_HO",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_MODE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_MODE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_MODE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_MODE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_LATCH_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_LATCH_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_LATCH_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_LATCH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_OVRR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_OVRR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_OVRR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_OVERRIDE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_EEE_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_EEE_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_EEE_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_EEE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PMD_X4_EEE_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PMD_X4_EEE_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PMD_X4_EEE_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PMD_X4_EEE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_ERROR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_MSA_25G_50G_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_MSA_25G_50G_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_MSA_25G_50G_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_MSA_25G_50G_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x30c, /* 780 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_DBG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_DBG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_DBG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_DEBUG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_SC_X4_OVRR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_SC_X4_OVRR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_SC_X4_OVRR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_SC_X4_OVERRIDE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_IEEE_25G_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_IEEE_25G_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_IEEE_25G_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_IEEE_25G_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x66, /* 102 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_BYPASS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_BYPASS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_BYPASS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_BYPASS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_SPARE0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_SPARE0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_SPARE0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_SPARE0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_SPARE1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_SPARE1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_SPARE1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_CONTROL_SPARE1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN0_TYPE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_FLD_OVRR_EN0_TYPE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN1_TYPE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_FLD_OVRR_EN1_TYPE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN2_TYPE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_FLD_OVRR_EN2_TYPE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_FLD_OVRR_EN2_TYPE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_SPD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_SPD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_SPD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_FEC_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_FEC_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_FEC_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SC_X4_RSLVD_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SC_X4_RSLVD_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SC_X4_RSLVD_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_CRED0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_CRED0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_CRED0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CREDIT0_CREDIT0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_CRED1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_CRED1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_CRED1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CREDIT0_CREDIT1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_LOOPCNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_LOOPCNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_LOOPCNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CREDIT0_LOOPCNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_MAC_CREDGENCNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_MAC_CREDGENCNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CREDIT0_MAC_CREDITGENCNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_ENC_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_ENC_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_ENC_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CONTROL0_ENCODE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1800, /* 6144 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_MISC_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_MISC_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_MISC_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CONTROL0_MISC",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1c0, /* 448 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_CL36_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_CL36_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_CL36_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CONTROL0_CL36TX_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_TX_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_TX_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_TX_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_CONTROL0_TX_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xb8, /* 184 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_ENC_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_ENC_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_ENC_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_STATUS0_ENCODE_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_ENC_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_ENC_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_ENC_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_STATUS0_ENCODE_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_PCS_STS_LIVE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_PCS_STS_LIVE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_STATUS0_PCS_STATUS_LIVE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCH_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_PCS_STS_LATCH_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_PCS_STS_LATCH_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_STATUS0_PCS_STATUS_LATCHED",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_X4_PMA_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_X4_PMA_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_X4_PMA_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_X4_STATUS0_PMA_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PCS_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PCS_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PCS_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_PCS_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_THR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_THR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_THR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_CL91_THRESHOLD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1a1, /* 417 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_TMR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_TMR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_TMR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_CL91_TIMER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xfa0, /* 4000 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_RX_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_RX_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_RX_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_CL91_RX_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_DEC_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_DEC_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_DEC_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_DECODE_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2270, /* 8816 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLKSYNC_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_BLKSYNC_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PMA_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PMA_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PMA_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_PMA_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_LNK_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_LNK_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_LNK_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_LINK_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL36_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL36_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL36_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_CL36RX_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIV_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_SYNCE_FRACTIONAL_DIV_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_SYNCE_FRACTIONAL_DIV_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x14a0, /* 5280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_IEEE_25G_PARLLEL_DET_CTR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_FEC_CONTROL_FEC_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x442c, /* 17452 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_FEC_CONTROL_FEC_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x28, /* 40 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_FEC_CONTROL_FEC_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7c00, /* 31744 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_FEC_CONTROL_FEC_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLKSYNC_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BLKSYNC_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLKSYNC_DBG0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BLKSYNC_DBG0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLKSYNC_DBG1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BLKSYNC_DBG1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLKSYNC_DBG2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLKSYNC_DBG2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BLKSYNC_DBG2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BLK_LOCK_LATCH_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BLK_LOCK_LATCH_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_AM_LOCK_LATCH_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_AM_LOCK_LATCH_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PCS_LIVE_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_PCS_LIVE_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BIPCNT_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BIPCOUNT_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BIPCNT_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BIPCOUNT_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_BIPCNT_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_BIPCNT_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_BIPCOUNT_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PSLL_TO_VL_MAP_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PSLL_TO_VL_MAP_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PSLL_TO_VL_MAP_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PRTPERRCTR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PRTPERRCTR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PRTPERRCTR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_PRTPERRORCOUNTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PRTPSTS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PRTPSTS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PRTPSTS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_PRTPSTATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FC_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FC_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FC_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS0_CL91_FC_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PCS_LATCH_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PCS_LATCH_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_PCS_LATCHED_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_PCS_LIVE_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_PCS_LIVE_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_PCS_LIVE_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_DEC_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_DECODE_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_DEC_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_DECODE_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_DEC_STS_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_DECODE_STATUS_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_DEC_STS_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_DEC_STS_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_DECODE_STATUS_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL36_SYNCACQ_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL36_SYNCACQ_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL36_SYNCACQ_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL36_BERCNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL36_BERCNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL36_BERCNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_CL36RX_BERCOUNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_IEEE_25G_PARLLEL_DET_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_IEEE_25G_PARLLEL_DET_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_IEEE_25G_PARLLEL_DET_STS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL49_SCRIDLE_TEST_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL49_SCRIDLE_TEST_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL49_SCRIDLE_TEST_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LATCH_STS_PSLL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LATCH_STS_PSLL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LATCH_STS_PSLL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LATCH_STS_PSLL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LATCH_STS_PSLL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LATCH_STS_PSLL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LIVE_STS_PSLL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LIVE_STS_PSLL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LIVE_STS_PSLL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LIVE_STS_PSLL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL82_AM_LIVE_STS_PSLL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL82_AM_LIVE_STS_PSLL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_SYNC_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_SYNC_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL91_SYNC_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_ST_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_SYNC_FSM_ST_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_SYNC_FSM_ST_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_FEC_SYNC_FSM_STATE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FC_SLIP_CNT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FC_SLIP_CNT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FC_SLIP_CNT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS2_CL91_FC_SLIP_CNT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRAH_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRAH_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRAH_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRAH_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRAH_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRAH_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRAH_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRAH_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_DBG_ERRAH_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_DBG_ERRAH_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_DBG_ERRAH_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSH_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSH_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSH_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSH_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BURST_ERR_STSH_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BURST_ERR_STSH_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSH_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSH_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSH_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSH_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORRBLKSH_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORRBLKSH_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSH_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSH_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSH_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSH_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORRBLKSH_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORRBLKSH_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TEST1_TXPKTCNT_U_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TEST1_TXPKTCNT_U_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TEST1_TXPKTCNT_U_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TEST1_TXPKTCNT_U",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TEST1_TXPKTCNT_L_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TEST1_TXPKTCNT_L_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TEST1_TXPKTCNT_L_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TEST1_TXPKTCNT_L",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TEST1_RXPKTCNT_U_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TEST1_RXPKTCNT_U_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TEST1_RXPKTCNT_U_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TEST1_RXPKTCNT_U",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TEST1_RXPKTCNT_L_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TEST1_RXPKTCNT_L_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TEST1_RXPKTCNT_L_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TEST1_RXPKTCNT_L",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_CL73_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_CL73_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_CL73_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_CL73_CFG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_UP1_ABIL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_UP1_ABILITIES_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_UP1_ABIL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_UP1_ABIL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_UP1_ABILITIES_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BASE_ABIL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BASE_ABILITIES_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2a1, /* 673 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BASE_ABIL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BASE_ABILITIES_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABIL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BAM_ABIL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BAM_ABIL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BAM_ABILITIES",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_CL73_CTLS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_CL73_CTLS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_CL73_CTLS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_CL73_CONTROLS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BASE_ABIL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BASE_ABILITIES_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BASE_ABIL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BASE_ABILITIES_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_BASE_ABIL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_BASE_ABIL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_BASE_ABILITIES_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_FEC_BASEPAGE_ABIL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_SW_AN_BASE_PAGE_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_SW_AN_BASE_PAGE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_SW_AN_BASE_PAGE_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_SW_AN_BASE_PAGE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_SW_AN_BASE_PAGE_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_SW_AN_BASE_PAGE_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_ABILITIES_SW_AN_BASE_PAGE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_R_CL73_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_R_CL73_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_R_CL73_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_R_CL73_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_PXNG_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_PXNG_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_PXNG_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_PXNG_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_PSEQ_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_PSEQ_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_PSEQ_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_PSEQ_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_PSEQ_RF_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_PSEQ_RF_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_PSEQ_RF_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_PSEQ_RF",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_UNEXP_PAGE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_UNEXP_PAGE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_UNEXP_PAGE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_BASE1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_BASE1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_BASE1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_BASE1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_BASE2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_BASE2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_BASE2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_BASE2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_BASE3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_BASE3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_BASE3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_BASE3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_OUI_UP1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_OUI_UP1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_OUI_UP2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_OUI_UP2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_OUI_UP3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_OUI_UP3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_OUI_UP4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_OUI_UP4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_OUI_UP5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_OUI_UP5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_LP_OUI_UP5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_RES_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_RES_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_RES_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_STATUS_RES_ERR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_PAGE_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LD_PAGE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_PAGE_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LD_PAGE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_PAGE_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_PAGE_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LD_PAGE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_PAGE_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LP_PAGE_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_PAGE_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LP_PAGE_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LP_PAGE_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LP_PAGE_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LP_PAGE_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_SW_CTL_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_SW_CTL_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_SW_CTL_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_SW_CONTROL_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_LD_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_LD_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_LD_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_LD_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_AN_ABIL_RESOLUTION_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_AN_ABIL_RESOLUTION_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x120, /* 288 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_AN_MISC_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_AN_MISC_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_AN_MISC_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_AN_MISC_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_TLA_SEQUENCER_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_TLA_SEQUENCER_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_INT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_INT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_INT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_INT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_INT_EN_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_INT_EN_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_INT_EN_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_INT_EN",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AN_X4_WAIT_ACK_COMPLETE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AN_X4_WAIT_ACK_COMPLETE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AN_X4_WAIT_ACK_COMPLETE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AN_X4_SW_MGMT_WAIT_ACK_COMPLETE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_ILKN_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_ILKN_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ILKN_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"ILKN_X4_CONTROL0_ILKN_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_ILKN_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_ILKN_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ILKN_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"ILKN_X4_STATUS0_ILKN_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x11, /* 17 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_ALGN_FSM_ST_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_ALGN_FSM_ST_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_ALGN_FSM_ST_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8, /* 8 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_RXP_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_RXP_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_RXP_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_CL91_RXP_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x600, /* 1536 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORR_CTR_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_CORR_CTR_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_CORR_CTR_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORR_CTR_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_UNCORR_CTR_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_UNCORR_CTR_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BIT_ERR_CTR_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_FEC_BIT_ERR_CTR_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_FEC_BIT_ERR_CTR_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_UP_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_UP_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_UP_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_LOW_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_CL91_FEC_SYM_ERR_CTR_UP_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_CL91_FEC_SYM_ERR_CTR_UP_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_CL91_BUFFER_BLK_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_CL91_BUFFER_BLK_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_CL91_BUFFER_BLK_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_DESKEW_MEM_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_DESKEW_MEM_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_DESKEW_MEM_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_DESKEW_MEM_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_STS_DESKEW_MEM_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_STATUS_DESKEW_MEM_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_1BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_1BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_INTR_STS_1BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_INTERRUPT_STATUS_1BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_2BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_STS_2BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_INTR_STS_2BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_INTERRUPT_STATUS_2BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_1BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_1BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_INTR_EN_1BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_INTERRUPT_EN_1BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3f, /* 63 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_2BIT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_INTR_EN_2BIT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_INTR_EN_2BIT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_INTERRUPT_EN_2BIT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3f, /* 63 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_DIS_ECC_MEM_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_DIS_ECC_MEM_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_DIS_ECC_MEM_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_DISABLE_ECC_MEM",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_RX_X4_ECC_CORRUPT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_RX_X4_ECC_CORRUPT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"RX_X4_ECC_CORRUPT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"RX_X4_ECC_CORRUPT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_ACC_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_ACC_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ACC_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_CL22_IEEE_COM_ACC_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_ACC_ADDR_DATA_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_ACC_ADDR_DATA_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ACC_ADDR_DATA_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_CL22_IEEE_COM_ACC_ADDR_DATA",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTL_150_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_CTL_150_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_PMD_CTL_150_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STS_151_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_PMD_STS_151_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_PMD_STS_151_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPD_152_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPD_152_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IR_BASE_R_LP_COEFF_UPD_152_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REP_153_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IR_BASE_R_LP_STS_REP_153_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IR_BASE_R_LP_STS_REP_153_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPD_154_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPD_154_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_LD_COEFF_UPD_154_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REP_155_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_IT_BASE_R_LD_STS_REP_155_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_LD_STS_REP_155_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PF_CTL_DC_OFFS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PF_CTL_DC_OFFS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RX_PF_CTRL_DC_OFFSET",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXA_SLCR_OFFS_ADJ_DN_DP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXA_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXA_SLCR_OFFS_ADJ_ZN_ZP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXA_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXAB_SLCR_OFFS_ADJ_LMS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXAB_SLICER_OFFSET_ADJ_LMS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXB_SLCR_OFFS_ADJ_DN_DP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXB_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXB_SLCR_OFFS_ADJ_ZN_ZP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXB_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXC_SLCR_OFFS_ADJ_DN_DP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXC_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXC_SLCR_OFFS_ADJ_ZN_ZP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXC_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXCD_SLCR_OFFS_ADJ_LMS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXCD_SLICER_OFFSET_ADJ_LMS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXD_SLCR_OFFS_ADJ_DN_DP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXD_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXD_SLCR_OFFS_ADJ_ZN_ZP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXD_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SEL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PHASE_LMS_THR_SEL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PHASE_LMS_THR_SEL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RX_PHASE_LMS_THRESH_SEL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_AB_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_AB_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP2_AB_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP2_AB",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP2_CD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP2_CD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP2_CD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_AB_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_AB_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP3_AB_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP3_AB",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP3_CD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP3_CD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP3_CD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP4_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP4_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP4_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP5_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP5_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP5_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP6_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP6_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP6_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP7_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP7_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP8_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP8_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP8_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP9_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP9_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP10_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP10_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP10_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP11_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP11_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP12_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP12_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP12_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP13_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP13_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP14_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP14_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP14_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP7_8_MUX_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP9_10_MUX_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP11_12_MUX_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP13_14_MUX_ABCD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_LOAD_PRESETS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_LOAD_PRESETS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_LOAD_PRESETS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_LOAD_PRESETS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_UC_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_UC_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_UC_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_A_DSC_UC_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SCRATCH_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SCRATCH_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SCRATCH_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_A_DSC_SCRATCH",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_A_LOW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_A_LOW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_A_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_A_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_A_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_A_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_A",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_B_LOW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_B_LOW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_B_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_B_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_B_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_B_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_B",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_C_LOW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_C_LOW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_C_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_C_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_C_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_C_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_C",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_D_LOW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_D_LOW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_D_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_D_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_D_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_D_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_D",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_LOW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_LOW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_LOW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_DC_OFFS_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_DC_OFFS_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DC_OFFS_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_DC_OFFSET_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_VGA_D_THR_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_VGA_D_THR_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_VGA_D_THR_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_VGA_D_THRESH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2700, /* 9984 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x9, /* 9 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x80, /* 128 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_RX_PI_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_PAT_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_PAT_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_PAT_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_PAT_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_PAT_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_TAP_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_TAP_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_TAP_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_TDT_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_TDT_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_TDT_CTL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_TRNSUM_MISC_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_TRNSUM_MISC_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_MISC_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_MISC",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_VGA_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_VGA_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_VGA_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_VGA_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_DATA_SLCR_THR_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DATA_SLCR_THR_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_DATA_SLICER_THRESH_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_DC_OFFS_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_DC_OFFS_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DC_OFFS_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_DC_OFFSET_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8, /* 8 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x200, /* 512 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x87, /* 135 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1c1e, /* 7198 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x35ad, /* 13741 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x340d, /* 13325 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x11, /* 17 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_CTL_9_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_CTL_9_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL_9_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCK_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_LOCK_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_LOCK_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_LOCK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_ONE_HOT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_ST_ONE_HOT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOT_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOT_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_ST_EEE_ONE_HOT_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_STS_RESTART_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_STS_RESTART_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_RESTART_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_RESTART",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_SM_STS_DSC_ST_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_ST_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_PD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_PD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_PD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_LD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_LD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_LD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DATA_15_TO_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DATA_15_TO_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_DATA_15_TO_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_DATA_35_TO_20_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DATA_35_TO_20_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_DATA_35_TO_20",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_STS_PHASE_ERR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_PHASE_ERR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_PHASE_ERROR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_D_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_D_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_D_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_D",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_P_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_P_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_P_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_P",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_L_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_RX_PI_CNT_BIN_L_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_L_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_L",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_STS_INTEG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_STS_INTEG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_INTEG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_INTEG_REG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_STS_MISC_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_STS_MISC_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_MISC_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_MISC",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_CDR_1G_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_CDR_1G_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_1G_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_1G_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DSC_PRESET_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DSC_PRESET_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_PRESET_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_PRESET_REG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x52, /* 82 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_CTL2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_CTL2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x310, /* 784 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_UC_INTR_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_INTR_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_INTERRUPT_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_UC_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UR_UC_STS1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_STS1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_STATUS1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_XMT_UPD_PAGE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_XMT_UPD_PAGE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_XMT_UPDATE_PAGE_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGE_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_LD_XMT_STS_PAGE_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_LD_XMT_STS_PAGE_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_LD_XMT_STATUS_PAGE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_CTL2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_CTL2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x500, /* 1280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_CTL3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_CTL3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL3_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2b, /* 43 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CL93N72_UT_CTL4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CL93N72_UT_CTL4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL4_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x23f5, /* 9205 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7000, /* 28672 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x100, /* 256 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_CTL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_PI_PMD_STS_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_CLK_RST_N_PWRDWN_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_AFE_RST_PWRDWN_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_AFE_RESET_PWRDWN_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_RST_N_PWRDN_PIN_KILL_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_DBG_RST_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_DBG_RST_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_DEBUG_RESET_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x303, /* 771 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_UC_ACK_LN_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_UC_ACK_LN_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_UC_ACK_LANE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_RST_OCC_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_RST_OCC_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_REG_RESET_OCCURRED_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_CLK_N_RST_DBG_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_CLK_N_RST_DBG_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_CLOCK_N_RESET_DEBUG_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_PMD_LN_MODE_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_PMD_LN_MODE_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_PMD_LANE_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_DP_RST_ST_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_DP_RST_ST_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_DP_RESET_STATE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_MCST_MASK_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_MCST_MASK_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_MCST_MASK_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_MULTICAST_MASK_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_OSR_MODE_PIN_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_PIN_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_PIN_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_CKRST_LN_S_RSTB_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_S_RSTB_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LN_S_RSTB_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x10, /* 16 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xe00, /* 3584 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_CTL_9_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_CTL_9_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL_9_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x300, /* 768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_RX_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_RX_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x14, /* 20 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_TX_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_TX_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc0, /* 192 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_TX_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_TX_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2000, /* 8192 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_TX_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_TX_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xf, /* 15 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_TX_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_TX_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_TX_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_TX_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x6a0, /* 1696 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SIGDET_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SIGDET_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1109, /* 4361 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SIGDET_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SIGDET_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa008, /* 40968 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SIGDET_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SIGDET_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3f22, /* 16162 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_SIGDET_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_SIGDET_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x200, /* 512 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_REVID0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_REVID0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2db, /* 731 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_RST_CTL_PMD_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_RST_CTL_PMD_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_CTL_PMD_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RESET_CONTROL_PMD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DP_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_RST_CTL_CORE_DP_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_CTL_CORE_DP_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RESET_CONTROL_CORE_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4000, /* 16384 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_CORE_MCST_MASK_CONRTOL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_CORE_MCST_MASK_CONRTOL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_CORE_MCST_MASK_CONRTOL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_CORE_MULTICAST_MASK_CONRTOL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_TOP_USER_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_TOP_USER_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TOP_USER_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TOP_USER_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x271, /* 625 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_UC_ACK_CORE_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_UC_ACK_CORE_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_UC_ACK_CORE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_CORE_RST_OCC_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_CORE_RST_OCC_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_RST_SEQ_TMR_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_SEQ_TMR_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RST_SEQ_TIMER_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8304, /* 33540 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_CORE_DP_RST_ST_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_CORE_DP_RST_ST_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_CORE_DP_RESET_STATE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_PMD_CORE_MODE_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_PMD_CORE_MODE_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_PMD_CORE_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_REVID1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_REVID1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x403c, /* 16444 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_TX_LN_MAP_0_1_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TX_LN_MAP_0_1_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TX_LANE_MAP_0_1_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x820, /* 2080 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TX_LN_MAP_3_N_LN_ADDR_0_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x403, /* 1027 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_LN_ADDR_2_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_LN_ADDR_2_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_LANE_ADDR_2_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x302, /* 770 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_DIG_REVID2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_DIG_REVID2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1e, /* 30 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x77, /* 119 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f00, /* 7936 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc1c0, /* 49600 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_CTL_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_CTL_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f00, /* 7936 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_AMS_PLL_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_AMS_PLL_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_8_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_8_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_8_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_9_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_9_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_9_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_10_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_10_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_10_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_10",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_11_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_11_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_11_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_11",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_12_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_12_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_12_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_12",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_13_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_13_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_13_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_13",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_14_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PATT_GEN_SEQ_14_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_14_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_14",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_CTL2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_CTL2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x500, /* 1280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_STS1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_STS1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2b, /* 43 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_STS2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_STS2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x500, /* 1280 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_STS3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_STS3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2b, /* 43 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_STS4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_STS4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_UC_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_UC_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_UC_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_MICRO_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TXFIR_MISC_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TXFIR_MISC_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_MISC_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_MISC_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x300, /* 768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc803, /* 51203 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc8ff, /* 51455 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff01, /* 65281 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_4_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_4_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_4_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa80d, /* 43021 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_5_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_5_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_5_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x27, /* 39 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_6_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_6_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_6_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_7_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_7_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_7_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS_0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS_1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_PLL_CAL_CTL_STS_DBG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS_DBG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_DBG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x70, /* 112 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_CTL2_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_CTL2_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL2_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f4, /* 500 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TX_CTL3_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TX_CTL3_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL3_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL3_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc8, /* 200 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CNT_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_CNT_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_CNT_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x602, /* 1538 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x10a, /* 266 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_DIG_LPBK_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_DIG_LPBK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa, /* 10 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_MISC_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_MISC_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_MISC_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_MISC_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_EN_TMR_CTL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_EN_TIMER_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_DIG_LPBK_PD_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_DIG_LPBK_PD_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_DIG_LPBK_PD_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_LOCK_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_LOCK_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_LOCK_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_ERR_CNT_MSB_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_ERR_CNT_LSB_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PMD_RX_LOCK_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PMD_RX_LOCK_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PMD_RX_LOCK_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_BURST_ERR_LEN_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_MAX_PRBS_BURST_ERR_LEN_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_TX_PATT_GEN_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_PATT_GEN_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_PATT_GEN_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xb000, /* 45056 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_TX_PRBS_GEN_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_PRBS_GEN_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_PRBS_GEN_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa, /* 10 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_RMT_LPBK_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_RMT_LPBK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_TX_MISC_CFG_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_TX_MISC_CFG_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_MISC_CFG_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_MISC_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STS_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_TLB_TX_RMT_LPBK_PD_STS_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_RMT_LPBK_PD_STS_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_RMT_LPBK_PD_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CLK_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CLK_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CLK_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_CLOCK_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RST_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RST_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RST_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_RESET_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_WRADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_WRADDR_MSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRADDR_MSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_WRDATA_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRDATA_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRDATA_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_WRDATA_MSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRDATA_MSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRDATA_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_RDADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_RDADDR_MSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDADDR_MSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_RDDATA_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDDATA_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDDATA_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_AHB_RDDATA_MSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDDATA_MSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDDATA_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_PRAMIF_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_PRAMIF_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_AHB_WRADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_PRAMIF_AHB_WRADDR_MSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_AHB_WRADDR_MSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_PVT_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_PVT_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PVT_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_PVT_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_TO_UC_MBOX0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_TO_MICRO_MBOX0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_TO_UC_MBOX1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_TO_UC_MBOX1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_TO_MICRO_MBOX1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_UC_TO_RMI_MBOX0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_MICRO_TO_RMI_MBOX0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_UC_TO_RMI_MBOX1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_UC_TO_RMI_MBOX1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_MICRO_TO_RMI_MBOX1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_MBOX_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_MBOX_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_MBOX_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_AHB_CTL1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_AHB_CTL1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_AHB_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_AHB_STS1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_AHB_STS1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_AHB_STS1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_AHB_STATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_RA_AINC_NXT_WRADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_RA_AINC_NXT_RDADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSW_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSW_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_PR_AINC_NXT_WRADDR_LSW_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_PVT_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_PVT_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_PVT_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCCTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCCONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCCONTRO1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCCONTRO1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCCONTRO1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCSTS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCSTATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CODE_RAM_ECCSTS1_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCSTS1_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCSTATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_CODE_RAM_TESTIFCTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_TESTIFCTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_TESTIFCONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RAM_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RAM_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RAM_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RAM_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x401, /* 1025 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_CTL0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_EXT_INTR_CTL0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RMI_EXT_INTR_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_UC_RMI_EXT_INTR_STS0_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_EXT_INTR_STS0_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RMI_EXT_INTR_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MDIO_MASKDATA_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MDIO_MASKDATA_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_MASKDATA_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_MASKDATA",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MDIO_BCST_PORT_ADDR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_BCST_PORT_ADDR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f, /* 31 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MDIO_MMD_SEL_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MDIO_MMD_SEL_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_MMD_SEL_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x404d, /* 16461 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MDIO_AER_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MDIO_AER_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_AER_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_AER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_TSCF_XGXS_MDIO_BLK_ADDR_GEN2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_TSCF_XGXS
	BCMI_TSCF_XGXS_MDIO_BLK_ADDR_GEN2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_BLK_ADDR_GEN2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_BLK_ADDR_COM_BLK_ADDR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
#endif
};


phymod_symbols_t bcmi_tscf_xgxs_gen2_symbols = 
{
   bcmi_tscf_xgxs_gen2_syms, sizeof(bcmi_tscf_xgxs_gen2_syms)/sizeof(bcmi_tscf_xgxs_gen2_syms[0]),
#if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1
   bcmi_tscf_xgxs_gen2_fields
#else
   NULL
#endif
/* END OF SYMBOL FILE */
};

#endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */
